PowerPC e500 Core Family Reference Manual, Rev. 1
13-10 Freescale Semiconductor
Core Complex Bus (CCB)
occurs though an interrupt controller that is reporting enabled interrupts from either the peripheral
block that detected the bus fault or from a watchdog timer.
Therefore, to ensure forward progress during normal operation, peripheral error-reporting logic
must be configured to signal an interrupt (such as int
or cint) for all possible sources of
core_fault_in
. Otherwise, the core stalls indefinitely on a bus fault, waiting for an interrupt.
However, during software or firmware development, when peripheral error-reporting may not yet
be properly configured, the core can be configured (by setting HID1[RFXE]) to generate a
machine check (or checkstop) on every assertion of core_fault_in
. This forces bus faulted
transactions to complete and allows processing to continue, even though little bus fault-specific
information is saved that indicates the cause of the machine check. This is the only instance where
RFXE should be set (except for the case for the e500v1, described in the HID1[RFXE] bit
description of Section 2.10.2, “Hardware Implementation-Dependent Register 1 (HID1)).
Care must be taken if HID1[RFXE] is set = 1 during debug and some sources of core_fault_in
are
configured to signal an interrupt to the core (through int
or cint), because in this case, two
interrupts (machine check and external) could be reported on a bus fault, but the less-specific
machine check interrupt enabled by RFXE = 1 (and MSR[ME] = 1) may occur first, giving little
information about the cause of the fault.
Therefore, for normal operation, RFXE should always be cleared so that bus faults associated with
peripheral devices do not generate a machine check interrupt or checkstop, but generate only the
more useful interrupt provided by the peripheral. Thus, peripheral error reporting for all possible
causes of core_fault_in
should always be enabled for normal operation.
See Section 11.3.4.5, “Speculative Accesses to Guarded Memory,” for a cautionary statement
regarding memory areas that are set up as both cacheable and guarded.
To Next Page
Loading...
