Freescale Semiconductor PowerPC e500 Core - Instruction Set

PowerPC e500 Core Family Reference Manual, Rev. 1
1-12 Freescale Semiconductor
Core Complex Overview
• Data cache flush assist capability, supported through HID0[DCFA]. When DCFA is set, the
cache miss replacement algorithm ignores invalid entries and follows the replacement
sequence defined by the PLRU bits. This reduces the series of uniquely addressed load or
dcbz instructions required to flush the cache.
Detailed descriptions of these differences are provided in their respective chapters.
NOTE
Unless otherwise indicated, references to e500 apply to both e500v1
and e500v2.
1.4 Instruction Set
The e500 implements the following instructions:
• The Book E instruction set for 32-bit implementations. This is composed primarily of the
user-level instructions defined by the PowerPC user instruction set architecture (UISA).
The e500 does not include Book E floating-point, load string, or store string instructions.
• The e500 supports the following implementation-specific instructions:
— Integer select APU. This APU consists of the Integer Select instruction (isel), which
functions as an if
-then-else statement that selects between two source registers by
comparison to a CR bit. This instruction eliminates conditional branches, decreases
latency, and reduces the code footprint.
— Performance monitor APU. Table 1-2 lists performance monitor APU instructions.
— Cache locking APU. This APU consists of the instructions described in Table 1-3.
— Machine check APU. This APU defines the Return from Machine Check Interrupt
instruction (rfmci).
Table 1-2. Performance Monitor APU Instructions
Name Mnemonic Syntax
Move from Performance Monitor Register mfpmr rD,PMRN
Move to Performance Monitor Register mtpmr PMRN,rS
Table 1-3. Cache Locking APU Instructions
Name Mnemonic Syntax
Data Cache Block Lock Clear dcblc CT, rA, rB
Data Cache Block Touch and Lock Set dcbtls CT, rA, rB
Data Cache Block Touch for Store and Lock Set dcbtstls CT, rA, rB
Instruction Cache Block Lock Clear icblc CT, rA, rB
Instruction Cache Block Touch and Lock Set icbtls CT, rA, rB