PowerPC e500 Core Family Reference Manual, Rev. 1
Index-2 Freescale Semiconductor
C–C Index
BTB locking APU, 4-23, 10-2–10-3
entry address register (BBEAR), 2-25
instructions, 3-63
instructions for locking, 10-2
operation, 4-11, 4-20–4-25
fetch group, 4-21
registers, 10-3
target address register (BBTAR), 2-25
Branch unit (BU)
branch prediction, 4-1, 4-11, 4-20–4-25
see also Branch target buffer (BTB)
completion, 4-18
debug events
branch taken (BRT), 8-12
execution timing, 4-18–4-25, 4-31
resources required to minimize stalls, 4-45
fetch/branch considerations, 4-45
resolution, 4-1
Breakpoints, see Instruction address compare registers
(IAC1–IAC4)
BUCSR (branch unit control and status register), 2-26
Bus faults, 2-30, 13-9
Byte ordering
byte-reverse instructions, 3-22
misaligned accesses and Endian (E) bit, 11-13
C
Caches
block diagram with core interface, 4-26, 11-3
cache block lock and unlock APU, 3-61, 11-19
effects on PLRU, 11-27
flash clearing of lock bits, 11-21
cache control
cache management instructions, 3-37–3-39, 11-10, 11-16
comparison by architecture/implementation, 11-16
effects on locked lines, 11-21
overview, 1-29
enabling/disabling, 11-18
flushing with dcbf or dcbz, 11-22
invalidating, 11-18
overview, 11-16
registers
L1 configuration register 0 (L1CFG0), 2-34
L1 configuration register 1 (L1CFG1), 2-35
WIMGE bits, see Memory/cache access attributes
(WIMGE bits)
coherency
4-state (MESI) coherency model, 11-7
coherency model, 11-9
coherency required bit (M bit), 11-12
global signaling, M bit , and snooping, 11-12
instruction cache coherency model, 11-8, 11-11
address aliasing errors, 11-8
maintaining in power down mode, 6-3
see also Memory/cache access attributes (WIMGE bits)
features of e500 L1 caches, 11-1
L2 cache
cache line locking, 11-19, 11-27, 13-2, 13-7
invalidating after a parity error, 11-27
operand to support L2 cache touch (CT=1), 3-37, 3-62
latency
cacheable loads from data cache, 11-4
instruction cache accesses, 4-13, 11-1
caching-inhibited accesses, 4-13
load/store unit (LSU) interactions, 4-25–4-27
store queue, 4-26
operation, 11-22
allocation on misses, 11-24
block replacement, 11-25
PLRU algorithm, 11-25, 11-26
cacheable loads and LSU, 11-4
data block push, 11-24
data cache block fills, 11-23
hits under misses, 11-6, 11-7
instruction cache block fills, 11-5, 11-23
misses and reloads, 11-23
store hit to a data cache block marked shared, 11-24
store miss merging, 11-4, 11-24
organization, 11-6
coupling with load/store unit (LSU), 11-3
L1 data cache, 11-6
L1 instruction cache, 11-7
overview, 1-20
parity checking, 5-17, 11-8
see also HID1 register
parity errors
parity error injection, 5-18, 11-9
see also Interrupt handling, interrupt types, machine
check interrupt
status bits (MESI) per line, 11-7, 11-10
Classes of instructions, 3-6
Coherency
cache coherency, overview, 1-29
see also Caches, coherency
Completion (instruction completion), 4-6
completion queue (CQ), 4-1, 4-14
considerations, 4-14
definition, 4-1, 4-8, 4-9
pairs of instructions, 4-47
resource requirements, 4-46
Conditional branch control, 3-23
Context synchronization, 3-11, 3-44
Conventions
execution timing terminology, 4-1
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