Index D–E
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Index-3
notational, 1-xxxiv
terminology, 1-xxxv
Core complex bus (CCB)
address streaming mode, 13-7
core interface unit, 11-5
L2 cache transactions, 13-7
memory ops boundary with mbar, 13-6
overview, 1-30, 13-1
parity checking, 13-5
signals described, 13-2
synchronization boundary with msync, 13-6
core_fault_in
signal and interrupts, 2-30, 13-9
CR (condition register), 2-9
bit and identification symbols, C-11
execution latencies, 4-33
logical instructions, 3-25, C-20
move to/from CR instructions, 3-26
simplified mnemonics, C-20
Critical input interrupt (cint
), 5-13
see also Interrupt handling
CSRR0–1 (critical save/restore reg’s 0–1), 2-18, 5-5
CTR (count register), 2-10
D
d, 1-xxxiv
DAC1–DAC2 (data address compare registers), 2-48
Data address compare, 2-48
debug events, 8-9
DAC modes, 8-10
effective address (EA) selection, 8-10
read/write selection, 8-9
user/supervisor selection, 8-10
Data cache, see Caches
Data organization in memory and data transfers, 3-1
Data TLB error interrupt, 5-27
see also Interrupt handling, interrupt types, TLB miss
DBCR0–DBCR2 (debug control registers), 2-46
DBSR (debug status register), 2-47
dcba, 3-38
dcbf, 3-38
dcbi, 3-40
dcbst, 3-38
dcbt, 3-38
dcbtst, 3-39
dcbz, 3-38
DEAR (data exception address register), 2-18, 5-5
Debug facilities
debug events, 8-6–8-14
branch taken, 8-12
data address compare, 8-9
instruction address compare, 8-7
instruction complete debug event, 8-12
interrupt taken debug event, 8-13
return debug event, 8-13
trap debug event, 8-11
unconditional debug event (UDE), 8-14
debug interrupts, 8-2
deviations from Book E debug model, 8-3
interrupts, 5-30
see also Interrupt handling
overview, 8-1
performance monitor uses, 7-1
programming model, 8-1
instructions used, 8-2
registers, 8-1
registers, 2-45–2-49
TAP controller, 8-4
Debug interrupt, 8-2
DEC (decrementer register), 2-16, 9-3
DECAR (decrementer auto-reload register), 2-16, 9-3
Decrementer
decrementer interrupt, 5-25
see also Interrupt handling
decrementer registers
DEC (decrementer register), 2-16, 9-3
DECAR (decrementer auto-reload register), 9-3
DECAR (decrementer auto-reload), 2-16
Dispatch, see Execution timing
D-L1TLB4K, see Memory management unit (MMU), TLBs
D-L1VSP, see Memory management unit (MMU), TLBs
Double-precision, see Embedded double-precision
floating-point (DPFP) APU
Doze mode, 6-2
see also Power management
DSI (data storage interrupt), 5-19–5-20
see also Interrupt handling
E
e500 overview, 1-1
auxiliary processing units (APUs), 1-3
features, 1-5
future upward compatibility and SPE APU, 1-3
Effective address (EA)
loads/stores, 3-18
operand placement and performance, 4-30
translation to real address, see Memory management unit
(MMU)
EIS, see Freescale Book E implementation standards (EIS)
Embedded double-precision floating-point (DPFP) APU,
2-1, 3-49, 3-59, 10-4
instructions, 1-13
interrupts, 5-32
see also Interrupt handling
Embedded single-precision floating-point (SPFP) APUs
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