PowerPC e500 Core Family Reference Manual, Rev. 1
Index-4 Freescale Semiconductor
E–E Index
instructions, 1-13, 3-2, 3-58
execution latencies, 4-38
interrupts, 5-3
FP data interrupt, 5-32
FP round interrupt, 5-32
see also Interrupt handling
SPE/FP unavailable interrupt, 5-31
Endianness
byte-reverse instructions, 3-22
little-endian pages, 2-42
ESR (exception syndrome register), 2-20, 5-5, 5-6
Event counting, see Performance monitor APU
Exceptions
definition, 5-1
exception handling, 1-20
extended model, 1-20
overview, 1-33
see also Interrupt handling
exception priorities, 5-37–5-39
exception syndrome register (ESR), 2-20, 5-5
exception type information
ESR or MCSR, 5-10
instruction exceptions that cause interrupts, 3-12, 5-8, 5-38
SPE exception bit (ESR[SPE]), 5-4, 5-7
types (more granular than interrupts)
data access exceptions, 5-12
byte ordering exception (DSI or ISI), 5-7, 5-12
cache locking exception (DSI), 5-12
lwarx or stwcx. with W = 1 exception, 5-12
debug exceptions, 5-12
illegal instr. exception (program interrupt), 5-6, 5-12,
5-24
instruction access exceptions (ISI), 5-12
machine check exception sources, 5-15–5-18
bus and L1 cache (parity) errors, 5-7, 5-16
cache parity error injection, 5-7, 5-18
permissions violations (DSI or ISI), 12-24
privileged instr. exception (program interrupt), 5-6, 5-12,
5-24
see also Interrupt handling, interrupt types
TLB misses (I or D TLB error interrupt), 5-12
TLB misses (TLB error interrupts—I or D), 12-2, 12-12,
12-20, 12-22, 12-23, 12-24
trap instr. exceptions (program interrupt), 5-6, 5-12, 5-24
Execution model
self-modifying code, 3-17
Execution synchronization, 3-11
Execution timing
branch instructions, 4-18–4-25
branch prediction, 4-1, 4-11, 4-20–4-25
see also Branch target buffer (BTB)
completion, 4-18
latencies, 4-31
resolution, 4-1
resources for resolution of branches, 4-45
cache-related latency, instruction cache, 4-13
CR execution latencies, 4-33
definitions, 4-1
completion, 4-1, 4-6, 4-8, 4-9
decode, 4-2, 4-9
dispatch, 4-2
fetch, 4-2, 4-6, 4-9
finish, 4-2
issue, 4-2, 4-9
stages, 4-3
write-back, 4-8
execution units, 4-10, 4-18
multiple cycle unit (MU)
instructions executed, 4-8
performance considerations, 4-48
single cycle units (SUs)
instructions executed, 4-8
performance considerations, 4-47
FP instructions, 4-29
execution latencies, 4-38
instruction fetch timing considerations, 4-12–4-13
instruction flow, 4-4, 4-11
instruction pipeline, 1-14
complete stage, 1-18
decode/dispatch stage, 1-17
definition, 4-2
execute stages, 1-18
fetch stages (2), 1-16
issue queues (BIQ, GIQ), 1-17
write-back stage, 1-18
instruction pipeline stages, 4-4–4-10
completion, 4-1, 4-6, 4-8, 4-9
completion queue (CQ), 4-1, 4-14
pairs of instructions that can complete together, 4-47
resource requirements, 4-46
decode/dispatch, 4-2, 4-6, 4-9
considerations, 4-14
resource requirements, 4-45
execute stage, 4-7, 4-9
fetch stage, 4-2, 4-6, 4-9
and branch considerations, 4-45
instruction queue (IQ), 4-6, 4-10
flow diagram, 4-4, 4-5
issue, 4-2, 4-7, 4-9
resource requirements, 4-46
write-back, 4-8, 4-9
instruction unit
instruction line fill buffer (ILFB), 11-5
integer instructions
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