Freescale Semiconductor PowerPC e500 Core - Critical Input Interrupt

Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-13
5.7.1 Critical Input Interrupt
A critical input interrupt occurs when no higher priority exception exists, a critical input exception
is presented to the interrupt mechanism, and MSR[CE] = 1. The specific definition of a critical
input exception is implementation-dependent but is typically caused by assertion of an
asynchronous signal that is part of the system. In addition to MSR[CE], implementations may
provide other ways to mask the critical input interrupt.
IVOR32 SPE/
embedded
floating-point
APU unavailable
SPE/embedded
floating-point APU
unavailable
SP — —
9
5-31
IVOR33 Embedded
floating-point
data
Embedded floating-point
data exception
SP — —
9
5-32
IVOR34 Embedded
floating-point
round
Embedded floating-point
round exception
SP — —
9
5-32
1
A = asynchronous, C = critical, SI = synchronous, imprecise, SP = synchronous, precise
2
In general, when an interrupt causes an ESR bit or bits to be set (or cleared) as indicated in the table, it also causes all other
ESR bits to be cleared. Special rules may apply for implementation-specific ESR bits
Legend:
xxx (no brackets) means ESR[xxx] is set.
[xxx] means ESR[xxx] could be set.
[xxx,yyy] means either ESR[xxx] or ESR[yyy] may be set, but never both.
{xxx,yyy} means either ESR[xxx] or ESR[yyy] may be set, or possibly both.
3
Although not part of Book E, system interrupt controllers commonly provide independent mask and status bits for critical input
and external input interrupt sources.
4
Machine check interrupts are not asynchronous or synchronous. See Section 5.7.2, “Machine Check Interrupt.”
5
Machine check status information is commonly provided as part of the system implementation but is not part of Book E.
6
Software must examine the instruction and the subject TLB entry to determine the exact cause of the interrupt.
7
Cache locking and cache locking exceptions are implementation-dependent.
8
Instruction complete and branch taken debug events are defined only for MSR[DE] = 1 for internal debug mode (DBCR0[IDM]
= 1). In other words, for internal debug mode with MSR[DE] = 0, instruction complete and branch taken debug events cannot
occur, no DBSR status bits are set, and no subsequent imprecise debug interrupt can occur.
9
EIS-defined exception
Table 5-6. Interrupt and Exception Types (continued)
IVOR Interrupt Type Exception Type
Exception
Class
1
ESR
2
Mask Bits Notes Page