PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor E-1
Appendix E
Revision History
This appendix provides a list of major differences between revisions of the PowerPC e500 Core
Reference Manual.
NOTE
While previous revisions of this manual covered only the e500v1 core,
referring to it simply as the e500 core, this revision includes coverage
of both the e500v1 and e500v2 cores. As a result, substantial portions
of the manual were altered.
E.1 Major Changes From Revision 0 to Revision 1
Table E-1. Revision History
Chapter or Section Description
Throughout Revised manual to include coverage of e500v2 core. See Section 1.3.1, “e500v2 Differences,” for
a list of key differences between the e500v1 and e500v2 cores.
The coverage of Book E and Freescale Book E MMU architecture (formerly in Chapter 13, Cache
and MMU Background) was removed. See the EREF: A reference for Freescale Book E and the
e500 Core for more information on this subject.
Section 1.9.1, “Address
Translation”
Replaced Figure 1-9 to reflect corrections to address translation bit compositions made in MMU
chapter. Added Figure 1-10 for the e500v2 core.
Chapter 2, “Register Model” Deleted MCSR bits 48–54.
Also removed “Recoverable” column of bit descriptions
Removed SHAREN/SHAREND references in MAS2 and MAS4.
Section 2.10.2, “Hardware
Implementation-Dependent
Register 1 (HID1)”
Modified description of HID1[RFXE]
Section 2.12.2, “MMU
Control and Status Register
0 (MMUCSR0)
Deleted bits 59–60. They are now reserved.
Section 2.12.5, “MMU Assist
Registers (MAS0–MAS4,
MAS6–MAS7)”
Modified MAS register descriptions to correspond to those of MMU chapter
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