Freescale Semiconductor PowerPC e500 Core - Instruction Fetch Timing Considerations; Interrupts Associated with Instruction Fetching; L1 and L2 TLB Access Times

PowerPC e500 Core Family Reference Manual, Rev. 1
4-12 Freescale Semiconductor
Execution Timing
4.3.2 Instruction Fetch Timing Considerations
Instruction fetch latency depends on the following factors:
• Whether the page translation for the effective address of an instruction fetch is in a TLB.
This is described in Section 4.3.2.1, “L1 and L2 TLB Access Times.”
• If a page translation is not in a TLB, an instruction TLB miss interrupt is taken.
Section 4.3.2.2, “Interrupts Associated with Instruction Fetching,” describes other
conditions that cause an instruction fetch to take an interrupt. General interrupt latency and
pipeline behavior are described in Section 4.3.4, “Interrupt Latency.”
• If an L1 instruction cache miss occurs, a memory transaction is required in which fetch
latency is affected by bus traffic and bus clock speed. These issues are discussed further in
Section 4.3.2.3, “Cache-Related Latency.”
4.3.2.1 L1 and L2 TLB Access Times
The L1 TLB arrays are checked for a translation hit in parallel with the on-chip L1 cache lookups
and incur no penalty on an L1 TLB hit. If the L1 TLB arrays miss, the access proceeds to the L2
TLB arrays. For L1 instruction address translation misses, the L2 TLB latency is at least 5 clocks;
for L1 data address translation misses, the L2 TLB latency is at least 6 clocks. These access times
may be longer, depending on arbitration performed by the L2 arrays for simultaneous instruction
L1 TLB misses, data L1 TLB misses, the execution of TLB instructions, and TLB snoop
operations (snooping of TLBINV operations on the CCB).
Note that when a TLBINV operation is detected, the L2 MMU arrays become inaccessible due to
the snooping activity caused by the TLBINV.
If the MMU is busy due to a higher priority operation, such as a tlbivax, instructions cannot be
fetched until that operation completes.
If the page translation is in neither TLB, an instruction TLB error interrupt occurs, as described in
Section 5.7.13, “Instruction TLB Error Interrupt.”
TLBs are described in detail in Chapter 12, “Memory Management Units.”
4.3.2.2 Interrupts Associated with Instruction Fetching
An instruction fetch can generate the following interrupts:
• An instruction TLB error interrupt occurs when the effective address translation for a fetch
is not found in the TLBs. This interrupt is described in detail in Section 5.7.13, “Instruction
TLB Error Interrupt.”