PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 7-1
Chapter 7
Performance Monitor
This chapter describes the performance monitor, which is generally defined by the Freescale
Book E implementation standards (EIS) and implemented as an APU on the e500 core. Although
the programming model is defined by the EIS, some features are defined by the e500
implementation, in particular, the events that can be counted.
References to e500 apply to both e500v1 and e500v2.
7.1 Overview
The performance monitor provides the ability to count predefined events and processor clocks
associated with particular operations, for example cache misses, mispredicted branches, or the
number of cycles an execution unit stalls. The count of such events can be used to trigger the
performance monitor interrupt.
The performance monitor can be used to do the following:
• Improve system performance by monitoring software execution and then recoding
algorithms for more efficiency. For example, memory hierarchy behavior can be monitored
and analyzed to optimize task scheduling or data distribution algorithms.
• Characterize processors in environments not easily characterized by benchmarking.
• Help system developers bring up and debug their systems.
The performance monitor uses the following resources:
• The performance monitor mark bit in the MSR (MSR[PMM]). This bit controls which
programs are monitored.
• The move to/from performance monitor registers (PMR) instructions, mtpmr and mfpmr.
• The external input, pm_event.
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