PowerPC e500 Core Family Reference Manual, Rev. 1
3-2 Freescale Semiconductor
Instruction Model
3.1.2 Alignment and Misaligned Accesses
The operand of a single-register memory access instruction has an alignment boundary equal to its
length. An operand’s address is misaligned if it is not a multiple of its width.
The concept of alignment is also applied more generally to data in memory. For example, a 12-byte
data item is said to be word-aligned if its address is a multiple of four.
Some instructions require their memory operands to have certain alignment. In addition, alignment
can affect performance. For single-register memory access instructions, the best performance is
obtained when memory operands are aligned.
Instructions are 32 bits (one word) long and must be word-aligned.
Memory operands for single-register memory access instructions have the characteristics
described in Table 3-1.
Note that lmw, stmw, lwarx, and stwcx. instructions that are not word aligned cause an alignment
exception.
3.1.3 e500 Floating-Point Implementation
The e500 does not implement the floating-point instructions as they are defined in Book E.
Attempts to execute a Book E–defined floating-point instruction result in an illegal instruction
exception.
The e500 implements the following:
• The vector single-precision floating-point APU supports single-precision vector (64-bit,
two 32-bit operand) instructions.
• The scalar single-precision floating-point APU supports single-precision floating-point
operations using the lower 32 bits of the GPRs.
• The scalar double-precision floating-point APU (implemented on the e500v2) supports
double-precision floating-point operations using both halves of the GPRs.
Table 3-1. Address Characteristics of Aligned Operands
Operand Operand Length Addr[60–63] if Aligned
Byte 8 bits xxxx
1
1
An x in an address bit position indicates that the bit can be 0 or 1
independent of the state of other bits in the address.
Half word 2 bytes xxx0
Word 4 bytes xx00
Double word 8 bytes x000
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