Freescale Semiconductor PowerPC e500 Core - About this Book

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xxxi
About This Book
The primary objective of this user’s manual is to describe the functionality of the e500 embedded
microprocessor core for software and hardware developers. This book is intended as a companion
to the EREF: A Reference for Freescale Book E and the e500 Core (hereafter referred to as EREF).
The e500 is a PowerPC™ processor.
Note that, while previous versions of this manual covered only the e500v1 core (and referred to it
simply as the e500 core), this version includes coverage of both the e500v1 and e500v2 cores.
Where the two cores diverge, the differences are clearly delineated.
Book E is a PowerPC architecture definition for embedded processors that ensures binary
compatibility with the user-instruction set architecture (UISA) portion of the PowerPC
architecture as it was jointly developed by Apple, IBM, and Motorola. The version of the
architecture jointly developed by Apple, IBM, and Motorola is referred to as the AIM version of
the PowerPC architecture.
This document distinguishes between the three levels of the architectural and implementation
definition, as follows:
• The Book E architecture. Book E defines a set of user-level instructions and registers that
are drawn from the user instruction set architecture (UISA) portion of the AIM definition
PowerPC architecture. Book E also include numerous other supervisor-level registers and
instructions as they were defined in the AIM version of the PowerPC architecture for the
virtual environment architecture (VEA) and the operating environment architecture (OEA).
Because Book E defines a much different model for operating system resources (such as
the MMU and interrupts), it defines many new registers and instructions.
• Freescale Book E implementation standards. In many cases, the Book E architecture
definition provides a very general framework, leaving many higher-level details up to the
implementation. To ensure consistency among its Book E implementations, Freescale has
defined implementation standards that provide an additional layer of architecture between
Book E and the actual devices.
• e500 implementation details. Each processor typically defines instructions, registers, bits
within registers, and other aspects that are more detailed than either the Book E definition
or the Freescale Book E implementation standards.
This book describes all of the instructions and registers implemented on the e500, including
those defined by Book E and those that are e500-specific.