Freescale Semiconductor PowerPC e500 Core

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PowerPC e500 Core Family Reference Manual, Rev. 1

xxx Freescale Semiconductor

Tables

Table

Number Title

Page

Number

C-17 Branch Instructions and Simplified Mnemonics that Incorporate CR Conditions ...............C-16

C-18 Simplified Mnemonics with Comparison Conditions...........................................................C-16

C-19 Simplified Mnemonics for bc and bca without Comparison Conditions or

LR Updating.....................................................................................................................C-17

C-20 Simplified Mnemonics for bclr and bcctr without Comparison Conditions

and LR Updating ..............................................................................................................C-18

C-21 Simplified Mnemonics for bcl and bcla with Comparison Conditions

and LR Updating ..............................................................................................................C-18

C-22 Simplified Mnemonics for bclrl and bcctrl with Comparison Conditions

and LR Updating ..............................................................................................................C-19

C-23 Word Compare Simplified Mnemonics ................................................................................C-20

C-24 Condition Register Logical Simplified Mnemonics .............................................................C-20

C-25 Standard Codes for Trap Instructions....................................................................................C-21

C-26 Trap Simplified Mnemonics .................................................................................................C-22

C-27 TO Operand Bit Encoding ....................................................................................................C-23

C-28 Additional Simplified Mnemonics for Accessing SPRGs....................................................C-24

C-29 Simplified Mnemonics..........................................................................................................C-26

D-1 Instructions (Binary) by Mnemonic....................................................................................... D-1

D-2 Instructions (Decimal and Hexadecimal) by Opcode .......................................................... D-22

D-3 Instructions (Binary) by Form.............................................................................................. D-35

E-1 Revision History .................................................................................................................... A-1

Freescale Semiconductor PowerPC e500 Core - Page 30