Freescale Semiconductor PowerPC e500 Core - Page 29

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xxix
Tables
Table
Number Title
Page
Number
11-2 L1 Data Cache Coherency State Transitions....................................................................... 11-10
11-3 L1 Instruction Cache Coherency State Transitions..............................................................11-11
11-4 Data Cache Snoop Coherency State Transitions................................................................. 11-12
11-5 Instruction Cache Snoop Coherency State Transitions....................................................... 11-12
11-6 Cache Instruction Comparison............................................................................................ 11-16
11-7 Failed Cache Events............................................................................................................ 11-17
11-8 L1 PLRU Replacement Way Selection ............................................................................... 11-25
11-9 PLRU Bit Update Rules...................................................................................................... 11-26
12-1 TLB Maintenance Programming Model............................................................................... 12-3
12-2 Page Sizes for L1VSPs and TLB1 (L2 MMU) on the e500 Core.........................................12-6
12-3 Index of TLBs ....................................................................................................................... 12-9
12-4 TLB Entry Bit Definitions for e500.................................................................................... 12-17
12-5 tlbivax EA Bit Definitions.................................................................................................. 12-21
12-6 TLB1 Entry 0 Values after Reset ........................................................................................ 12-25
12-7 Registers Used for MMU Functions ................................................................................... 12-25
12-8 MAS0 Field Descriptions—MMU Read/Write and Replacement Control ........................ 12-26
12-9 MAS1 Field Descriptions—Descriptor Context and Configuration Control...................... 12-27
12-10 MAS2 Field Descriptions—EPN and Page Attributes .......................................................12-28
12-11 MAS3 Field Descriptions–RPN and Access Control ......................................................... 12-29
12-12 MAS4 Field Descriptions—Hardware Replacement Assist Configuration........................ 12-30
12-13 MAS6—TLB Search Context Register 0............................................................................ 12-31
12-14 MAS7 Field Descriptions—High Order RPN .................................................................... 12-31
12-15 MMU Assist Register Field Updates .................................................................................. 12-32
13-1 Summary of Selected Internal Signals.................................................................................. 13-2
C-1 Subtract Immediate Simplified Mnemonics ...........................................................................C-2
C-2 Subtract Simplified Mnemonics..............................................................................................C-2
C-3 Word Rotate and Shift Simplified Mnemonics .......................................................................C-3
C-4 Branch Instructions .................................................................................................................C-4
C-5 BO Bit Encodings ...................................................................................................................C-6
C-6 BO Operand Encodings ..........................................................................................................C-6
C-7 CR0 and CR1 Fields as Updated by Integer Instructions .......................................................C-9
C-8 BI Operand Settings for CR Fields for Branch Comparisons...............................................C-10
C-9 CR Field Identification Symbols...........................................................................................C-11
C-10 Branch Simplified Mnemonics .............................................................................................C-11
C-11 Branch Instructions ...............................................................................................................C-12
C-12 Simplified Mnemonics for bc and bca without LR Update..................................................C-13
C-13 Simplified Mnemonics for bclr and bcctr without LR Update............................................C-13
C-14 Simplified Mnemonics for bcl and bcla with LR Update ....................................................C-14
C-15 Simplified Mnemonics for bclrl and bcctrl with LR Update...............................................C-14
C-16 Standard Coding for Branch Conditions...............................................................................C-15