Freescale Semiconductor PowerPC e500 Core - Page 28

PowerPC e500 Core Family Reference Manual, Rev. 1
xxviii Freescale Semiconductor
Tables
Table
Number Title
Page
Number
5-16 Alignment Interrupt Register Settings .................................................................................. 5-23
5-17 Program Interrupt Exception Conditions.............................................................................. 5-24
5-18 Program Interrupt Register Settings...................................................................................... 5-24
5-19 System Call Interrupt Register Settings................................................................................ 5-25
5-20 Decrementer Interrupt Register Settings............................................................................... 5-25
5-21 Fixed-Interval Timer Interrupt Register Settings.................................................................. 5-26
5-22 Watchdog Timer Interrupt Register Settings......................................................................... 5-27
5-23 Data TLB Error Interrupt Exception Conditions .................................................................. 5-27
5-24 Data TLB Error Interrupt Register Settings.......................................................................... 5-28
5-25 MMU Assist Register Field Updates for TLB Error Interrupts............................................ 5-28
5-26 Instruction TLB Error Interrupt Exception Conditions.........................................................5-29
5-27 Instruction TLB Error Interrupt Register Settings ................................................................ 5-29
5-28 Debug Interrupt Register Settings......................................................................................... 5-30
5-29 SPE/Embedded Floating-Point APU Unavailable Interrupt Register Settings..................... 5-31
5-30 Embedded Floating-Point Data Interrupt Register Settings.................................................. 5-32
5-31 Embedded Floating-Point Round Interrupt Register Settings...............................................5-33
5-32 Operations to Avoid .............................................................................................................. 5-36
6-1 Power Management Signals of Core Complex....................................................................... 6-1
6-2 Core Power States ................................................................................................................... 6-3
6-3 Core Power Management Control Bits ................................................................................... 6-3
7-1 Performance Monitor Registers–Supervisor Level................................................................. 7-2
7-2 Performance Monitor Registers–User Level (Read-Only) .....................................................7-3
7-3 PMGC0 Field Descriptions.....................................................................................................7-4
7-4 PMLCa0–PMLCa3 Field Descriptions................................................................................... 7-6
7-5 PMLCb0–PMLCb3 Field Descriptions .................................................................................. 7-7
7-6 PMC0–PMC3 Field Descriptions ........................................................................................... 7-8
7-7 Performance Monitor APU Instructions ................................................................................. 7-9
7-8 Processor States and PMLCa0–PMLCa3 Bit Settings.......................................................... 7-11
7-9 Event Types........................................................................................................................... 7-13
7-10 Performance Monitor Event Selection.................................................................................. 7-13
8-1 Debug SPRs ............................................................................................................................ 8-1
8-2 Debug Interrupt Register Settings........................................................................................... 8-3
8-3 DBCR0 and DBSR Field Differences..................................................................................... 8-4
8-4 TAP/IEEE/JTAG Interface Signal Summary.......................................................................... 8-5
8-5 JTAG Signal Details................................................................................................................8-6
8-6 Debug Events .......................................................................................................................... 8-7
8-7 Instruction Address Compare Modes...................................................................................... 8-8
8-8 Data Address Compare Modes ............................................................................................. 8-10
10-1 BTB Locking APU Instructions............................................................................................ 10-2
11-1 Cache Line State Definitions .............................................................................................. 11-10