Freescale Semiconductor PowerPC e500 Core - Page 27

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xxvii
Tables
Table
Number Title
Page
Number
3-30 TLB Management Instructions ............................................................................................. 3-41
3-31 Implementation-Specific Instructions Summary .................................................................. 3-43
3-32 e500-Specific Instructions (Except SPE and SPFP Instructions) .........................................3-43
3-33 Natural Alignment Boundaries for Extended Vector Instructions ........................................ 3-44
3-34 SPE APU Vector Multiply Instruction Mnemonic Structure................................................ 3-52
3-35 Mnemonic Extensions for Multiply-Accumulate Instructions.............................................. 3-53
3-36 SPE APU Vector Instructions ............................................................................................... 3-53
3-37 Vector and Scalar Floating-Point APU Instructions ............................................................. 3-59
3-38 Integer Select APU Instruction ............................................................................................. 3-60
3-39 Performance Monitor APU Instructions ............................................................................... 3-60
3-40 e500-Defined PMR Encodings ............................................................................................. 3-61
3-41 Cache Locking APU Instructions ......................................................................................... 3-61
3-42 Machine Check APU Instruction .......................................................................................... 3-63
3-43 Branch Target Buffer (BTB) Instructions ............................................................................. 3-63
3-44 List of Instructions ................................................................................................................3-66
4-1 Load and Store Queues ......................................................................................................... 4-26
4-2 The Effect of Operand Size on Divide Latency.................................................................... 4-27
4-3 Branch Operation Execution Latencies................................................................................. 4-31
4-4 System Operation Instruction Execution Latencies.............................................................. 4-31
4-5 Condition Register Logical Execution Latencies.................................................................. 4-33
4-6 SU and MU PowerPC Instruction Execution Latencies ....................................................... 4-33
4-7 LSU Instruction Latencies ....................................................................................................4-35
4-8 SPE and Embedded Floating-Point APU Instruction Latencies ........................................... 4-38
4-9 Natural Alignment Boundaries for Extended Vector Instructions ........................................ 4-49
4-10 Data Cache Miss, L2 Cache Hit Timing ............................................................................... 4-50
5-1 SPE APU Unavailable Interrupt Generation When MSR[SPE] = 0.......................................5-3
5-2 Interrupt Registers Defined by the PowerPC Architecture..................................................... 5-5
5-3 Exception Syndrome Register (ESR) Definition .................................................................... 5-6
5-4 Machine Check Syndrome Register (MCSR) Field Descriptions .......................................... 5-7
5-5 Asynchronous and Synchronous Interrupts ............................................................................ 5-9
5-6 Interrupt and Exception Types .............................................................................................. 5-12
5-7 Critical Input Interrupt Register Settings.............................................................................. 5-14
5-8 e500 Machine Check Exception Sources.............................................................................. 5-15
5-9 Machine Check Interrupt Settings......................................................................................... 5-16
5-10 Parity Error Exception Scenarios.......................................................................................... 5-17
5-11 Data Storage Interrupt Exception Conditions ....................................................................... 5-19
5-12 Data Storage Interrupt Register Settings............................................................................... 5-20
5-13 Instruction Storage Interrupt Exception Conditions ............................................................. 5-20
5-14 Instruction Storage Interrupt Register Settings..................................................................... 5-21
5-15 External Input Interrupt Register Settings ............................................................................ 5-22