Freescale Semiconductor PowerPC e500 Core - User Local Control a Registers (Upmlca0-Upmlca3); Local Control B Registers (Pmlcb0-Pmlcb3)

PowerPC e500 Core Family Reference Manual, Rev. 1
7-6 Freescale Semiconductor
Performance Monitor
PMLCa registers are cleared by a hard reset. Table 7-4 describes PMLCa fields.
7.2.4 User Local Control A Registers (UPMLCa0–UPMLCa3)
The PMLCa contents are reflected to UPMLCa0–UPMLCa3, which can be read by user-level
software with mfpmr using PMR numbers in Table 7-2.
7.2.5 Local Control B Registers (PMLCb0–PMLCb3)
Local control B registers 0 through 3 (PMLCb0–PMLCb3) specify a threshold value and a
multiple to apply to a threshold event selected for the corresponding performance monitor counter.
For the e500, thresholding is supported only for PMC0 and PMC1. PMLCb works with the
corresponding PMLCa register.
Table 7-4. PMLCa0–PMLCa3 Field Descriptions
Bits Name Description
32 FC Freeze counter.
0 The PMC can be incremented (if enabled by other performance monitor control fields).
1 The PMC cannot be incremented.
33 FCS Freeze counter in supervisor state.
0 The PMC can be incremented (if enabled by other performance monitor control fields).
1 The PMC cannot be incremented if MSR[PR] is cleared.
34 FCU Freeze counter in user state.
0 The PMC can be incremented (if enabled by other performance monitor control fields).
1 The PMC cannot be incremented if MSR[PR] is set.
35 FCM1 Freeze counter while mark is set.
0 The PMC can be incremented (if enabled by other performance monitor control fields).
1 The PMC cannot be incremented if MSR[PMM] is set.
36 FCM0 Freeze counter while mark is cleared.
0 The PMC can be incremented (if enabled by other performance monitor control fields).
1 The PMC cannot be incremented if MSR[PMM] is cleared.
37 CE Condition enable.
0 Overflow conditions for PMC
n cannot occur (PMC n cannot cause interrupts or freeze counters)
1 Overflow conditions occur when the most-significant-bit of PMC
n is equal to 1.
It is recommended that CE be cleared when counter PMC
n is selected for chaining.
38–40 — Reserved, should be cleared.
41–47 EVENT Event selector. Up to 128 events selectable. See Section 7.7, “Event Selection”
48–63 — Reserved, should be cleared.