Freescale Semiconductor PowerPC e500 Core - Load Miss Pipeline

PowerPC e500 Core Family Reference Manual, Rev. 1
4-50 Freescale Semiconductor
Execution Timing
If a load misses in the L1 data cache, critical data forwarding occurs, followed shortly by the rest
of the cache line.
4.7.6.3.3 Load Miss Pipeline
As shown in Figure 4-10, the e500v1 supports as many as four outstanding load misses in the load
miss queue (LMQ); the e500v2 LMQ supports as many as nine. Table 4-10 shows a load followed
by a dependent add. Here, the load misses in the data cache and the full line is reloaded into the
data cache.
Table 4-10. Data Cache Miss, L2 Cache Hit Timing
Instruction0123456
lwz r4,0x0(r9) E0 E1 Miss LMQ0 LMQ0/E2 C
add r5,r4,r3————— E C