Freescale Semiconductor PowerPC e500 Core - Chapter 10 Auxiliary Processing Units (Apus); Overview

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 10-1
Chapter 10
Auxiliary Processing Units (APUs)
This chapter describes the e500 APU support. It fully describes those APUs that are specific to the
e500 and the double-precision floating-point APU implemented on the e500v2. Full descriptions
of the APUs defined by the Freescale Book E implementation standards (EIS) are provided in the
EREF: A Reference for Freescale Book E and the e500 Core (EREF).
References to e500 apply to both e500v1 and e500v2.
10.1 Overview
The e500 supports the following APUs defined by the EIS:
• Integer select APU
• Performance monitor APU
• Signal processing engine APU (SPE APU)
• Embedded floating-point APUs
— Embedded vector single-precision floating-point APU
— Embedded scalar single-precision floating-point APUs
— Embedded scalar double-precision floating-point APUs. See 10.4, “Double-Precision
Floating-Point APU (e500 v2 Only).”
Note that the e500 diverges from the architected definition provided in the EREF. Details
are provided in Section 3.8.1.4, “Embedded Floating-Point APU Instructions,” and in
Section 2.5.1, “Machine State Register (MSR).”
• Cache block lock and unlock APU
• Machine check APU
• The e500v2 supports the alternate time base APU, described in Section 10.3, “Alternate
Time Base APU.”