PowerPC e500 Core Family Reference Manual, Rev. 1
8-12 Freescale Semiconductor
Debug Support
8.4.4 Branch Taken Debug Event
A branch taken debug event occurs if both MSR[DE] and DBCR0[BRT] are set (branch taken
debug events are enabled) and execution is attempted of a branch instruction whose direction is
taken (an unconditional branch or a conditional branch whose branch condition is met).
Because branch instructions occur very frequently, branch taken debug events are not recognized
if MSR[DE] is cleared when the branch instruction executes and thus DBSR[IDE] cannot be set
by a branch taken debug event. Allowing these common events to be recorded as exceptions in the
DBSR while debug interrupts are disabled would cause an inordinate number of imprecise debug
interrupts.
The following actions are taken when a branch taken debug event occurs:
• DBSR[BRT] is set (to capture the debug exception).
• A debug interrupt occurs immediately (if no higher priority exception has caused an
interrupt).
• Execution of the exception-causing instruction is suppressed.
• CSRR0 is set to the address of the excepting instruction.
8.4.5 Instruction Complete Debug Event
An instruction complete debug event occurs when any instruction completes execution so long as
MSR[DE] and DBCR0[ICMP] are both set (instruction complete debug events are enabled). Note
that no instruction complete debug event occurs if execution of an instruction is suppressed
because it caused some other interrupt-generating exception. The sc instruction does not fall into
the category of an instruction whose execution is suppressed, because the instruction actually
completes execution and then generates a system call interrupt. In this case, the instruction
complete debug exception is also set.
Instruction complete debug events are not recognized if MSR[DE] is cleared at the time of the
instruction execution. DBSR[IDE] cannot be set by an instruction complete debug event because
allowing the common instruction completion event to log an exception in the DBSR while debug
interrupts are disabled would cause the debug interrupt handler software to receive an inordinate
number of imprecise debug interrupts whenever debug interrupts were reenabled.
The following actions are taken when an instruction complete debug event occurs:
• DBSR[ICMP] is set (to record the debug exception).
• A debug interrupt occurs immediately (if no higher priority exception has caused an
interrupt).
• CSRR0 is set to the address of the instruction following the one that caused the instruction
complete debug exception.
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