PowerPC e500 Core Family Reference Manual, Rev. 1
B-2 Freescale Semiconductor
Guidelines for 32-Bit Book E
• 64-bit extended addressing load instructions—lbze, lbzue, lbzxe, lbzxue, ldarxe, lde,
ldue, ldxe, ldxue, lfde, lfdue, lfdxe, lfdxue, lfse, lfsue, lfsxe, lfsxue, lhae, lhaue, lhaxe,
lhaxue, lhbrxe, lhze, lhzue, lhzxe, lhzxue, lwarxe, lwbrxe, lwze, lwzue, lwzxe, lwzxue
• 64-bit extended addressing store instructions—stbe, stbue, stbxe, stbxue, stdcxe., stde,
stdue, stdxe, stdxue, stfde, stfdue, stfdxe, stfdxue, stfiwxe, stfse, stfsue, stfsxe, stfsxue
,
sthbrxe, sthe, sthue, sthxe, sthxue, stwbrxe, stwcxe., stwe, stwue, stwxe, stwxue
B.2 Registers on 32-Bit Book E Implementations
Book E defines 32- and 64-bit registers. All 32-bit registers are supported as defined in Book E.
However, only bits 32–63 of Book E’s 64-bit registers are required to be implemented in hardware
in 32-bit Book E implementation. Such 64-bit registers include LR, CTR, 32 GPRs, SRR0, and
CSRR0. Book E makes no restrictions regarding implementing a subset of the 64-bit
floating-point architecture.
Likewise, other than floating-point instructions, all instructions defined to return a 64-bit result
return only bits 32–63 of the result on a 32-bit Book E implementation.
B.3 Addressing on 32-Bit Book E Implementations
Only bits 32–63 of the 64-bit Book E instruction and data memory effective addresses need to be
calculated and presented to main memory. Given that only branch and data memory access
instructions not included in Section B.1, “64-Bit–Specific Book E Instructions,” are defined to
prepend 32 zeros to bits 32–63 of the effective address computation, a 32-bit implementation can
bypass the prepending of the 32 zeros when implementing these instructions. For branch to LR
and branch to CR instructions, given that LR and CTR are implemented as 32-bit registers,
concatenating only 2 zeros to the right of bits 32–61 of these registers is necessary to form the
32-bit branch target address.
The simplest implementation of next sequential instruction address computation suggests
allowing effective address computations to wrap from 0xFFFF_FFFC to 0x0000_0000. This
wrapping is required of PowerPC implementations. For 32-bit Book E applications, there appears
little if any benefit to allowing this wrapping behavior. Book E specifies that the situation where
the computation of the next sequential instruction address after address 0xFFFF_FFFC is
undefined (note that the next sequential instruction address after address 0xFFFF_FFFC on a
64-bit Book E implementation is 0x0000_0001_0000_0000).
B.4 TLB Fields on 32-bit Book E Implementations
32-bit Book E implementations should support bits 32–53 of the effective page number (EPN)
field in the TLB. This size provides support for a 32-bit effective address, which PowerPC ABIs
may have come to expect to be available. 32-bit Book E implementations may support greater than
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