Freescale Semiconductor PowerPC e500 Core - Timer Registers

PowerPC e500 Core Family Reference Manual, Rev. 1
2-14 Freescale Semiconductor
Register Model
2.6 Timer Registers
The time base (TB), decrementer (DEC), fixed-interval timer (FIT), and watchdog timer provide
timing functions for the system. The e500 provides the ability to select any of the TB bits to trigger
watchdog and fixed-interval timer events, as shown in Figure 2-5.
Figure 2-5. Relationship of Timer Facilities to the Time Base
e500 registers involved in timing are described as follows:
• The TB is a long-period counter driven at an implementation-dependent frequency.
• The decrementer, updated at the same rate as the TB, provides a way to signal an exception
after a specified period unless one of the following occurs:
— DEC is altered by software in the interim.
— The TB update frequency changes.
DEC is typically used as a general-purpose software timer.
• The time base for the TB and DEC is selected by the time base enable (TBEN) and select
time base clock (SEL_TBCLK) bits in HID0, as follows:
— If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8 bus
clocks.
— If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is updated on the
rising edge of tbclk (or an implementation-specific clock input).
• Software can select one from of four TB bits to signal a fixed-interval interrupt whenever
the bit transitions from 0 to 1. It is typically used to trigger periodic system maintenance
functions. Bits that may be selected are implementation-dependent.
Timer Clock
Time Base (incrementer)
Decrementer event = 0/1 detect
63
DECAR
32
Auto-reload
6332
TBL
6332
TBU
Watchdog timer events based on one of the TB bits
selected by the EIS–defined TCR[WPEXT] concatenated
with the Book E–defined TCR[WP] (WPEXT || WP).
Fixed-interval timer events based on one of TB bits
selected by the EIS–defined TCR[FPEXT] concatenated
with the Book E–defined TCR[FP] (FPEXT || FP).
DEC
(Time Base Clock)
tbclk