Freescale Semiconductor PowerPC e500 Core - Cache-Related Latency

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-13
• An instruction storage interrupt is caused when one of the following occurs during an
attempt to fetch instructions:
— An execute access control exception is caused when one of the following conditions
exist:
– In user mode, an instruction fetch attempts to access a memory location that is not
user mode execute enabled (page access control bit UX = 0).
– In supervisor mode, an instruction fetch attempts to access a memory location that is
not supervisor mode execute enabled (page access control bit SX = 0).
— A byte ordering exception occurs when the implementation cannot fetch the instruction
in the byte order specified by the page’s endian attribute. On the e500, accesses that
cross a page boundary such that endianness changes causes a byte ordering exception.
When an instruction storage interrupt occurs, the processor suppresses execution of the
instruction causing the exception. For more information, see Section 5.7.4, “Instruction
Storage Interrupt.”
4.3.2.3 Cache-Related Latency
The following may happen when instructions are fetched from the instruction cache,:
• If the fetch hits the cache, it takes 2 clock cycles after the request for as many as four
instructions to enter the IQ. The cache is not blocked to internal accesses during a cache
reload (hits under misses).
The cache allows a hit under one miss and is only blocked by a cache line reload for the
cycle during the cache write. For example, if a cache miss is discarded by a misprediction
and a new fetch hits, the cache allows instructions to come back. As many as four
instructions per cycle are fetched from the cache until the original miss comes back and a
cache reload is performed, which blocks the cache for 1 cycle.
If the cache is busy due to a higher priority operation, such as an icbi or a cache line reload,
instructions cannot be fetched until that operation completes.
• If an instruction fetch misses the on-chip instruction cache, the e500 initiates a core
complex bus transaction to the non-core memory system.
To minimize the effect of bus contention, the Book E architecture defines WIM bits that define
caching characteristics for the corresponding page. Accesses to caching-inhibited memory
locations never update the L1 caches.
If a cache-inhibited access hits in the cache, the cache block is invalidated. If the cache block is
marked modified, it is copied back to memory before being invalidated. Where caching is
permitted, memory is configured as either write-back or write-through, as described in
Section 11.3.4, “WIMGE Settings and Effect on L1 Caches
.”