Freescale Semiconductor PowerPC e500 Core - E500 Interrupt Definitions

PowerPC e500 Core Family Reference Manual, Rev. 1
5-2 Freescale Semiconductor
Interrupts and Exceptions
defines the critical input, watchdog timer, debug, and machine check interrupts as critical
interrupts, but the EIS defines a third set of resources for the machine check interrupt, as
described below.
• Machine check interrupt—The EIS defines a separate set of resources for the machine check
interrupt, which is similar to the Book E–defined critical interrupt type. Machine check
interrupts on an EIS device use the machine check save and restore registers
(MCSRR0/MCSRR1) to save state when they are taken, and they use the rfmci instruction
to restore state. These interrupts can be masked by the machine check enable bit, MSR[ME].
All interrupts except the machine check interrupt are ordered within the two categories of
noncritical and critical, such that only one interrupt of each category is reported, and when it is
processed (taken), no program state is lost. Because save/restore register pairs are serially
reusable, program state may be lost when an unordered interrupt is taken. (See Section 5.10,
“Interrupt Ordering and Masking”.)
All interrupts except the machine check interrupt are context synchronizing as defined in the
instruction model chapter of the EREF. A machine check interrupt acts like a
context-synchronizing operation with respect to subsequent instructions.
5.2 e500 Interrupt Definitions
This section gives an overview of additions and modifications to the Book E interrupt model
defined by the EIS and implemented on the e500. Specific details are also provided throughout
this chapter. Except for the following, the core complex reports exceptions as specified in Book E:
• The machine check exception differs as follows:
— It is not processed as a critical interrupt, but uses MCSRR0 and MCSRR1 for saving the
return address and the MSR in case the machine check is recoverable.
— Return From Machine Check Interrupt instruction (rfmci) is implemented to support
the return to the address saved in MCSRR0.
— A machine check syndrome register, MCSR, is used to log the cause of the machine
check (instead of ESR). See Section 2.7.2.4, “Machine Check Syndrome Register
(MCSR),” for a description of the MCSR.
The core complex reports the machine check exception as described in Section 5.7.2,
“Machine Check Interrupt.”