Interrupts and Exceptions
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 5-3
• The following interrupts are defined for use with the embedded floating-point and
signal-processing (SPE) APUs:
— SPE/embedded floating-point unavailable interrupt. IVOR32 (SPR 528) contains the
vector offset. See Section 5.7.15.1, “SPE/Embedded Floating-Point APU Unavailable
Interrupt.”
— Embedded floating-point data interrupt. IVOR33 (SPR 529) contains the vector offset.
See Section 5.7.15.2, “Embedded Floating-Point Data Interrupt.”
— Embedded floating-point round interrupt. IVOR34 (SPR 530) contains the vector offset.
See Section 5.7.15.3, “Embedded Floating-Point Round Interrupt.”
The following additional bits are defined to support SPE and SPFP exceptions:
— MSR[38] is defined as the vector available bit (SPE). If this bit is clear and software
attempts to execute any of the SPE instructions, the SPE unavailable interrupt is taken.
If this bit is set, software can execute any SPE instructions.
NOTE
On the e500v1, all SPFP instructions also require MSR[SPE] to be set.
Any attempt to execute a vector or scalar SPFP instruction when
MSR[SPE] is 0 causes an SPE APU unavailable interrupt. On the
e500v2, when MSR[SPE] is 0, this interrupt is caused by DPFP
instructions and SPFP vector instructions, but not by SPFP scalar
instructions (in other words, only those instructions that access the
upper half of the GPRs).
Table 5-1 presents this information in table form.
For more information, see the “Embedded Vector and Scalar
Single-Precision Floating-Point APU Instructions,” section of the
“Instruction Model” chapter of the EREF.
Table 5-1. SPE APU Unavailable Interrupt Generation When MSR[SPE] = 0
APU e500v1 e500v2
SPE x x
Single-Precision Floating-Point Vector x x
Single-Precision Floating-Point Scalar x —
Double-Precision Floating-Point N/A x
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