Freescale Semiconductor PowerPC e500 Core - L2 TLB Arrays

Memory Management Units
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 12-11
12.3.2 L2 TLB Arrays
The level 1 MMUs are backed up by a unified level 2 MMU that translates both instruction and
data addresses. Like each L1 MMU, the L2 MMU consists of two TLB arrays:
• TLB1: a 16-entry, fully associative array that supports nine (e500v1) or eleven (e500v2)
page sizes.
• TLB0: a 256-entry, 2-way (e500v1) or 512-entry, 4-way (e500 v2) set associative array that
supports only 4-Kbyte page sizes.
The two L2 TLBs on the e500v1, which are the only TLBs accessible to the software, are shown
in Figure 12-6.
Figure 12-6. L2 MMU TLB Organization—e500v1
0
15
TLB1
V
0
Select
Compare
Compare
way 1
way 0
MUX
RPN
hit
V
Compare
Compare
RPN
hit
TLB0
Real Address
(translated bits,
depending on page size)
Virtual Addresses
VAs
127