Freescale Semiconductor PowerPC e500 Core - Default Chapter; Table of Contents

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor v
Contents
Paragraph
Number Title
Page
Number
Co nt ents
About This Book
Audience....................................................................................................................... xxxii
Organization.................................................................................................................. xxxii
Suggested Reading....................................................................................................... xxxiii
General Information............................................................................................. xxxiii
Related Documentation ....................................................................................... xxxiv
Conventions ................................................................................................................. xxxiv
Terminology Conventions..............................................................................................xxxv
Part I
e500 Core
Chapter 1
Core Complex Overview
1.1 Overview.......................................................................................................................... 1-1
1.1.1 Upward Compatibility ................................................................................................. 1-3
1.1.2 Core Complex Summary ............................................................................................. 1-3
1.2 e500 Processor and System Version Numbers................................................................. 1-5
1.3 Features............................................................................................................................ 1-5
1.3.1 e500v2 Differences.................................................................................................... 1-11
1.4 Instruction Set................................................................................................................1-12
1.5 Instruction Flow.............................................................................................................1-14
1.5.1 Initial Instruction Fetch.............................................................................................. 1-14
1.5.2 Branch Detection and Prediction............................................................................... 1-14
1.5.3 e500 Execution Pipeline ............................................................................................ 1-16
1.6 Programming Model...................................................................................................... 1-18
1.7 On-Chip Cache Implementation.................................................................................... 1-20
1.8 Interrupts and Exception Handling................................................................................ 1-20
1.8.1 Exception Handling ................................................................................................... 1-20
1.8.2 Interrupt Classes ........................................................................................................ 1-21
1.8.3 Interrupt Types........................................................................................................... 1-21
1.8.4 Upper Bound on Interrupt Latencies ......................................................................... 1-22
1.8.5 Interrupt Registers...................................................................................................... 1-22
1.9 Memory Management.................................................................................................... 1-24
1.9.1 Address Translation ................................................................................................... 1-26
1.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7).....................................1-27