Freescale Semiconductor PowerPC e500 Core - Page 4

I Part I—e500 Core
1 Core Complex Overview
2 Register Model
3 Instruction Model
41Execution Timing
5 Interrupts and Exceptions
6 Power Management
7 Performance Monitor
8 Debug Support
II Part II—e500 Core Complex
9 Timer Facilities
10 Auxiliary Processing Units (APUs)
11 L1 Caches
12 Memory Management Units
13 Core Complex Bus (CCB)
A Appendix A—Programming Examples
B Appendix B—Guidelines for 32-Bit Book E
C Appendix C—Simplified Mnemonics for PowerPC Instructions
D Appendix D—Opcode Listings
E Appendix E—Revision History
IND Index