Auxiliary Processing Units (APUs)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 10-3
10.2.1.2 BTB Locking APU Registers
The BTB APU register model includes the following register resources for enabling the locking
and unlocking of BTB entries:
• Branch unit control and status register (BUCSR)—SPR 1013. This register has bits that are
used to enable or disable BTB locking and to control unlocking, invalidation, and
overlocking of BTB entries. See Section 2.9.3, “Branch Unit Control and Status Register
(BUCSR).”
• Branch buffer entry address register (BBEAR)—SPR 512. This register holds the address of a
BTB entry. See Section 2.9.1, “Branch Buffer Entry Address Register (BBEAR).”
• Branch buffer target address register (BBTAR)—SPR 513. This register includes branch
target address bits and a field that allows the programmer to specify whether a branch
should be predicted as taken or not taken. See Section 2.9.2, “Branch Buffer Target Address
Register (BBTAR).”
• MSR[UBLE], the user branch locking enable bit, determines whether user mode programs
can lock or unlock BTB entries. See Section 2.5.1, “Machine State Register (MSR).”
10.3 Alternate Time Base APU
The alternate time base APU defines a time base counter similar to the time base defined in
PowerPC architecture. It is intended to be used for measuring time in implementation-defined
intervals. It differs from the PowerPC defined time base in that it is not writable, it counts at a
different frequency, and it always counts up, wrapping when the 64-bit count overflows.
10.3.1 Programming Model
The alternate time base is a 64-bit counter that counts up at an implementation-dependent rate.
While not required, the rate is encouraged to be at the core clock frequency or as small a multiple
of the frequency as practical for the implementation. On the e500v2, this frequency is the core
frequency.
The ATBU and ATBL registers can be read by executing a mfspr instruction, but cannot be
written. Reading the ATB (or ATBL) register places the lower 32 bits of the counter into the target
register. A second SPR, ATBU, is defined that accesses only the upper 32 bits of the counter. Thus
the upper 32 bits of the counter may be read into a register by reading the ATBU register regardless
of computation mode.
ATB registers are described in Section 2.6.6, “Alternate Time Base Registers (ATBL and ATBU).”
The effect of power-savings mode or core frequency changes on counting in the alternate time base
is implementation-dependent. See the User’s Manual for details.
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