PowerPC e500 Core Family Reference Manual, Rev. 1
2-2 Freescale Semiconductor
Register Model
– CR0 can be set as the implicit result of an integer instruction.
– A specified CR field can be set as the result of an integer or floating-point compare
instruction (including SPE and SPFP compare instructions).
See Section 2.4.1, “Condition Register (CR).”
— The EIS-defined accumulator, used by the SPE APU. See Section 2.14.2, “Accumulator
(ACC).”
• Performance monitor registers (PMRs). Similar to SPRs, PMRs are accessed by using the
EIS-defined Move to Performance Monitor Register (mtpmr) and Move from Performance
Monitor Register (mfspr) instructions. See Section 2.15, “Performance Monitor Registers
(PMRs).”
2.2 e500 Register Model
The following sections describe the e500 core register model as defined in Book E and the
additional implementation-specific registers unique to the e500 core. Figure 2-1 shows the e500
register set and identifies which are defined by Book E, which are defined by the EIS, and which
are e500-specific.
Book E processors implement the following types of software-accessible registers:
• Book E–defined registers that are accessed as part of instruction execution. These include
the following:
— Registers used for integer operations:
– General-purpose registers (GPRs)—Book E defines a set of 32 GPRs used to hold
source and destination operands for load, store, arithmetic, and computational
instructions, and to read and write to other registers.
– Integer exception register (XER)—Bits in this register are set based on the operation
of an instruction considered as a whole, not on intermediate results. (For example,
the Subtract from Carrying instruction (subfc), the result of which is specified as the
sum of three values, sets bits in the XER based on the entire operation, not on an
intermediate sum.)
These registers are described in Section 2.3, “Registers for Integer Operations.”
— Condition register (CR)—Used to record conditions such as overflows and carries that
occur as a result of executing arithmetic instructions (including those implemented by
the SPE and SPFP APUs). The CR is described in Section 2.4, “Registers for Branch
Operations.”
— Machine state register (MSR)—Used by the operating system to configure parameters
such as user/supervisor mode, address space, and enabling of asynchronous interrupts.
MSR is described in Section 2.5.1, “Machine State Register (MSR).”
To Next Page
Loading...
