PowerPC e500 Core Family Reference Manual, Rev. 1
xxvi Freescale Semiconductor
Tables
Table
Number Title
Page
Number
2-32 DBCR1 Implementation-Specific Field Descriptions...........................................................2-46
2-33 DBCR2 Implementation-Specific Field Descriptions...........................................................2-47
2-34 DBSR Implementation-Specific Field Descriptions............................................................. 2-48
2-35 SPEFSCR Field Descriptions................................................................................................ 2-50
2-36 Performance Monitor Registers—Supervisor Level............................................................. 2-52
2-37 Performance Monitor Registers—User Level (Read-Only) .................................................2-53
2-38 PMGC0 Field Descriptions................................................................................................... 2-54
2-39 PMLCa0–PMLCa3 Field Descriptions................................................................................. 2-55
2-40 PMLCb0–PMLCb3 Field Descriptions ................................................................................ 2-56
2-41 PMC0–PMC3 Field Descriptions ......................................................................................... 2-57
2-42 Synchronization Requirements for SPRs.............................................................................. 2-58
3-1 Address Characteristics of Aligned Operands ........................................................................ 3-2
3-2 Unsupported Book E Instructions (32-Bit)............................................................................. 3-4
3-3 Data Access Synchronization Requirements .......................................................................... 3-8
3-4 Synchronization Requirements for e500-Specific SPRs......................................................... 3-8
3-5 Instruction Fetch and/or Execution Synchronization Requirements....................................... 3-9
3-6 Integer Arithmetic Instructions ............................................................................................. 3-14
3-7 Integer 32-Bit Compare Instructions (L = 0) ........................................................................ 3-15
3-8 Integer Logical Instructions .................................................................................................. 3-15
3-9 Integer Rotate Instructions.................................................................................................... 3-16
3-10 Integer Shift Instructions....................................................................................................... 3-16
3-11 Integer Load Instructions ...................................................................................................... 3-20
3-12 Integer Store Instructions...................................................................................................... 3-21
3-13 Integer Load and Store with Byte-Reverse Instructions ....................................................... 3-22
3-14 Integer Load and Store Multiple Instructions ....................................................................... 3-23
3-15 BO Bit Descriptions.............................................................................................................. 3-23
3-16 BO Operand Encodings ........................................................................................................3-23
3-17 Branch Instructions ............................................................................................................... 3-24
3-18 Condition Register Logical Instructions ............................................................................... 3-25
3-19 Trap Instructions ...................................................................................................................3-25
3-20 System Linkage Instruction ..................................................................................................3-26
3-21 Move to/from Condition Register Instructions..................................................................... 3-26
3-22 Move to/from Special-Purpose Register Instructions........................................................... 3-26
3-23 Book E Special-Purpose Registers (by SPR Abbreviation).................................................. 3-27
3-24 Implementation-Specific SPRs (by SPR Abbreviation) ....................................................... 3-29
3-25 Memory Synchronization Instructions.................................................................................. 3-30
3-26 User-Level Cache Instructions.............................................................................................. 3-38
3-27 System Linkage Instructions—Supervisor-Level ................................................................. 3-40
3-28 Move to/from Machine State Register Instructions .............................................................. 3-40
3-29 Supervisor-Level Cache Management Instruction................................................................ 3-41
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