Index F–I
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Index-5
execution latencies, 4-27, 4-33
issue queues (BIQ and GIQ), 4-6
GPR issue queue (GIQ), 4-46
latencies, 4-31–??
load/store instructions
execution latencies, 4-29, 4-35
LSU considerations
caches and pipelining in queues, 4-48
misalignment effects, 4-30, 4-49
memory performance considerations, 4-30
rename register operation, 4-7, 4-11, 4-15
scheduling guidelines, 4-44–4-50
SPE instruction latencies, 4-38
synchronization timing considerations, 4-17–4-18
mbar, 4-17
msync, 4-17
Execution units
see also Execution timing
timing examples, 4-18
F
Features list, 1-5
Fetch group, 4-21
see also Branch target buffer (BTB)
Fetch, see Execution timing
Finish definition, see Execution timing, definitions
Fixed-interval timer, 9-1
fixed-interval timer interrupt, 5-26
see also Interrupt handling
Floating-point model, 3-58
embedded double-precision (DPFP) instructions, 3-49,
3-59
execution timing, 4-29
interrupt handling, see Interrupt handling, interrupt types,
EIS-defined
single-precision (SPFP) instructions, 3-49
Fractions
integer and fractional operations, 3-52
signed fractions, format, 3-51
Freescale Book E architecture
interrupt model modifications, 5-2, 5-5, 5-6, 5-7, 5-8, 5-13,
5-14, 5-19, 5-20, 5-22, 5-24, 5-27, 5-28, 5-31
interrupt registers, 5-6–5-7
interrupts and APUs
embedded single-precision floating-point (SPFP) APUs,
5-3
machine check interrupt APU, 5-2
see also Auxiliary processing units (APUs)
signal processing engine (SPE) APU, 5-3
Freescale Book E implementation standards (EIS)
oveview, 1-3
G
Global accesses
signaling and snooping, 11-12
GPR issue queue (GIQ), 4-6, 4-46
GPRn (general-purpose registers 0–31), 2-9
Guarded memory (G bit), 12-16
see also Memory/cache access attributes (WIMGE bits)
H
Halted state, see Power management, core states
HIDn (hardware implementation-dependent registers)
HID0, 2-27, 9-2
HID1, 2-29
I
I/O accesses
ordering boundary with mbar, 13-6
IAC1–IAC2 (instruction address compare registers), 2-48
icbi, 3-39
icbt, 3-39
I-L1TLB4K, see Memory management unit (MMU), TLBs
I-L1VSP, see Memory management unit (MMU), TLBs
ILFB (instruction line fill buffer), 4-6
see also Execution timing, instruction fetch
Instruction address compare
as breakpoints, 2-48
debug event, 2-46
debug events
effective address (EA) selection, 8-8
IAC modes, 8-8
user/supervisor selection, 8-7
Instruction cache, see Caches
Instruction complete debug event, 8-12
Instruction fetching, see Execution timing
Instruction queue (IQ), 4-6, 4-10
see also Execution timing, instruction fetch
Instruction set
compatibility, 1-32
complete listing, 3-66
overview, 1-12, 3-13
summary, 3-5
Instruction TLB error interrupt, 5-29
see also Interrupt handling, interrupt types, TLB miss
Instructions
bbelr, 3-64
bblels, 3-65
Book E
64-bit–specific, B-1
Book E, see Book E architecture
branch, 4-18–4-25
condition register logical, 3-25
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