PowerPC e500 Core Family Reference Manual, Rev. 1
Index-6 Freescale Semiconductor
I–I Index
conditional branch control, 3-23
predicting and resolution, 4-20
simplified mnemonics, C-4
branch target buffer (BTB), 3-63
branch target buffer (BTB) locking, 10-2
cache block lock and unlock instructions, 3-61
cache management instructions, 1-29, 11-10
supervisor, 3-40
user, 3-37–3-39
classes, one of four, 3-6
context synchronization, 3-11
e500-specific, 3-43
exceptions, 3-12
execution latencies, see Execution timing
execution synchronization, 3-11
floating-point, 1-13, 3-2, 3-58
compare, C-20
see also Embedded double-precision floating-point
see also SPE, and SPFP
flow diagram for e500, 4-5
incorrect settings, 3-6
integer
arithmetic, 3-13
compare, 3-15, C-20
logical, 3-15
rotate and shift, 3-16
rotate/shift, C-2
store, 3-21
isel (instruction select) APU, 3-25, 3-60
load and store, 3-17
address generation, 3-18
byte reverse, 3-22
execution latencies, 4-35
ld/st multiple, 3-22
load instructions, 3-20
memory synchronization, 3-30
misalignment handling, 3-17
store instructions, 3-21
memory synchronization, 3-48
reservations with lwarx and stwcx., 3-32–3-37, 3-48
no-op, C-24
performance monitor, 7-9
processor control, 3-26–3-29
move to/from CR, 3-26
move to/from MSR, 3-40
move to/from SPR, 3-26
refetch serialization, 4-16
serialization, 4-15, 4-47
SPE (signal processing engine) APU, 3-52
SPE and SPFP descriptions, 3-49
speculative instructions, 4-3
SPFP (single-precision floating-point) APUs, 3-58
store serialization, 4-16
system linkage, 3-26, 3-40
system register instruction latencies, 4-31
TLB management instructions, 3-41, 12-17–12-24
synchronization requirements, 3-10
trap, 3-25
unsupported, 3-3
update feature for loads and stores, 3-47
int
(external input) interrupt, 5-21
see also Interrupt handling
Integer exception register (XER), 2-9
Integer instructions, 3-13–3-16
execution latencies, 4-27, 4-33
rotate/shift instructions, C-2
Interrupt classes
categories, 1-21
Interrupt handling
cache-inhibited stwcx. with bus error, 5-40
categories of interrupts
critical interrupts, 5-1
machine check interrupt APU (EIS), 5-2
see also Interrupt handling, interrupt types, machine
check interrupt
noncritical interrupts, 5-1
classes of interrupts
asynchronous interrupts, 5-9
synchronous, imprecise, 5-10
synchronous, precise, 5-9
debug event (interrupt taken), 8-13
definition of ’interrupt’, 5-1
guarded load pending with bus error, 5-40
guidelines for system software, 5-36
interrupt priorities
e500-specific priorities, 5-39
ordering of interrupts and masking, 5-37
interrupt types, 1-21
alignment interrupt, 5-22
critical input interrupt (cint
), 5-13
debug interrupt, 8-2, 8-3
debug interrupts, 5-30
decrementer, 5-25
DSI (data storage interrupt), 5-19–5-20, 12-24
EIS-defined
embedded floating-point data interrupt, 5-32
embedded floating-point round interrupt, 5-32
SPE/FP APU unavailable interrupt, 5-31
external input interrupt (int
), 5-21–5-22
fixed-interval timer, 5-26
instruction-caused interrupts, 3-12
ISI (instruction storage interrupt), 5-20–5-21, 12-24
machine check interrupt, 1-22, 2-30, 5-2, 5-14–5-18,
13-9
To Next Page
Loading...
