Index J–M
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Index-7
performance monitor interrupt, 5-33, 7-1, 7-10
program interrupt, 5-24–5-25
summary table, 5-12
system call, 5-25
TLB error, 12-2, 12-12, 12-20, 12-22, 12-23
data TLB error interrupt, 5-27
handler routines, 12-24
instruction TLB error interrupt, 5-29
MAS register updates for TLB error interrupts, 5-28
watchdog timer, 5-27
IVOR assignments, 5-12
latencies (upper bound), 1-22, 4-16, 5-39
machine check interrupt APU, 3-63
ordering of interrupts and masking, 5-35–5-37
overview, 5-1
power management considerations, 6-6
processing of interrupts, 5-10
instructions to consider in interrupt handler, 5-11
partially executed instructions, 5-33
recoverability from interrupts, 5-4
registers, 5-5–5-7
critical save/restore 0–1 (CSRR0–1), 2-18, 5-5
data exception address (DEAR), 2-18
data exception address register (DEAR), 5-5
debug settings, 8-3
defined by Book E for interrupts, 2-18, 5-5–5-6
defined by Freescale Book E for interrupts, 5-6–5-7
e500-specific, 2-22
exception syndrome register (ESR), 2-20, 5-5, 5-6
machine check address register (MCAR), 2-22, 5-6, 5-17
machine check save/restore 0–1 (MCSRR0–1), 2-22, 5-6
machine check syndrome (MCSR), 2-23
machine check syndrome register (MCSR), 5-6, 5-7
machine state register (MSR), 2-10, 5-6
overview, 1-22
save/restore 0–1 (SRR0–1), 2-18, 5-5
vector offset registers (IVOR0–IVOR15,
IVOR32–IVOR35), 2-19, 5-5
vector prefix (IVPR32–IVPR47), 2-19, 5-5
Interrupt taken debug event, 8-13
IPROT invalidation protection, 12-12
see also Memory management unit (MMU), TLBs
isel (instruction select) APU, 3-25, 3-60
ISI (instruction storage interrupt), 5-20
see also Interrupt handling
Issue stage, see Execution timing
isync, 3-30
IVOR0–IVOR15, IVOR32–IVOR35 (vector offset
registers), 2-19, 5-5
IVPR32–IVPR47 (vector prefix registers), 2-19, 5-5
J
JTAG signals, 8-5, 13-3
details, 8-6
L
L1 and L2 TLB access times, 4-12
L1 data cache, see Caches
L1 instruction cache, see Caches
L1CFG0 (L1 cache configuration register 0), 2-34
L1CFG1 (L1 cache configuration register 1), 2-35
L2 cache
CT value in cache line locking, 11-19, 11-27, 13-2, 13-7
CT value in cache touch instructions, 3-37, 3-62
invalidating after a parity error, 11-27
Latency, definition, 4-2
List insertion, A-6
Load miss queue (LMQ), 4-50
see also Load/store unit (LSU)
Load/store unit (LSU), 11-3
address generation, 3-18
byte reverse instructions, 3-22
cacheable loads
execution, 11-4
latency, 11-4
data line fill buffer (DLFB), 11-4
data write buffer (DWB), 11-5
execution latencies, 4-25–4-27, 4-29, 4-35
laod miss queue (LMQ), 4-50
store queue, 4-26
L1 load miss queue (LMQ), 11-4
ld/st multiple instructions, 3-22
load instructions, 3-20
misalignment handling, 3-17
operation, 4-25, 11-14
performed loads and stores, definition, 11-14
store instructions, 3-21
store ordering
mbar to enforce store ordering with respect to loads,
11-15, 13-6
store queue (7-entry), 11-4
Lock acquisition and release, A-5
Locking lines in the caches, see Caches, cache block lock and
unlock APU
LR (link register), 2-10
lwarx, 3-30, 3-48, 11-15, 13-8
M
Machine check interrupt APU, 1-22, 3-63, 5-14–5-18
see also Interrupt handling
MAS0–MAS4, MAS6–MAS7 (MMU assist registers), 1-27,
2-39–2-45, 12-26–12-31
To Next Page
Loading...
