PowerPC e500 Core Family Reference Manual, Rev. 1
Index-8 Freescale Semiconductor
M–M Index
mbar, 3-30, 3-47, 4-17, 13-6
MCAR (machine check address register), 2-22, 5-6, 5-17
mcp
input, 5-7
see also Interrupt handling, interrupt types, machine check
interrupt
MCSR (machine check syndrome register), 2-23, 5-6, 5-7
MCSRR0–1 (machine check save/restore reg’s 0–1), 2-22,
5-6
Memory management unit (MMU)
address translation (EA to real address), 12-4
page sizes, variable-sized pages (VSPs), 12-6
virtual addresses and PIDs (process IDs), 12-5
features, 12-1
instructions, 12-17–12-24
tlbivax (invalidate), 12-20, 12-21
tlbre (read entry), 12-18
tlbsx (search), 12-19
tlbsync (synchronize), 12-22
tlbwe (write entry), 12-19
overview, 1-24, 1-33
process IDs (PID0–2), 12-5, 12-21
registers, 2-35–2-45, 12-25–12-32
MAS register updates, 12-32
process ID (PID0–2), 12-5, 12-21
TLBs, 12-8–12-25
access times, 4-12, 12-16
consistency between L1, L2 TLB arrays, 12-15
default TLB entries (on reset), 12-24
error on multiple TLB entry hit, 12-8, 12-15
field definitions of TLB entries, 12-17
fields compared to determine a hit, 12-7
access permissions, 12-7
fields on 32-bit Book E implementations, B-2
instructions, 3-41, 11-11
invalidation
invalidate all address encoding, 12-22
invalidate broadcast enabling, 12-22
invalidate selection for tlbivax, 12-21
IPROT (protect from invalidate), 12-12
L1 TLB arrays (not programmable), 12-8
D-L1TLB4K, 12-8
D-L1VSP, 12-8
I-L1TLB4K, 12-8
I-L1VSP, 12-8
replacement algorithm (true LRU), 12-10
structure, 12-9
L2 TLB arrays (programmable), 12-8
replacement algorithm (general), 12-13
replacement algorithm, hints for round robin (TLB0),
12-13
structure, 12-11
TLB0 (4 Kbyte page sizes), 12-11, 12-18
TLB1 (variable page sizes), 12-11, 12-15, 12-18
maintenance, 12-3, 12-18, 12-22
misses (TLB error interrupts), 12-2, 12-12, 12-20, 12-22
automatic updates, 12-23
handler routines, 12-24
synchronization requirements, 3-6, 3-10
TLB coherency, 1-28
writing to TLB0, 12-19
writing to TLB1, 12-19
Memory model
access ordering, 1-29, 3-45
alignment support, 3-44
atomic updates, 1-29
data organization and transfers, 3-1
reservations, 3-32–3-37, 3-45, 3-48
sequential consistency of accesses, 11-15
and mbar, 3-47, 13-6
synchronization boundary with msync, 3-46, 13-6
Memory subsystem
overview, 1-33
Memory synchronization, 3-30
synchronization instructions, 3-48
Memory/cache access attributes (WIMGE bits), 1-30
caching-inhibited accesses (I bit), 2-42, 11-13
ci
internal signal, 13-2
Endianness (little-endian) bit (E bit), 2-42, 11-13
guarded memory bit (G bit), 2-42
guarded memory, 12-16
speculative accesses, 11-13
L1 caches effects, 11-13
memory coherency required bit (M bit), 2-42, 11-12
gbl
internal signal, 13-3
write-through mode (W bit), 2-42
write-back stores, 11-13
write-through stores, 11-13
wt
internal signal, 13-3
mfmsr, 3-40
mfspr, 3-26
Misaligned accesses, 3-2, 4-49, 11-13
MMUCFG (MMU configuration register), 2-37
MMUCSR0 (MMU control and status register), 2-36
Mnemonics
recommended, C-24
simplified, C-1
MSR (machine state register), 2-10, 5-6
move to/from MSR instructions, 3-40
writing to MSR[EE], 3-40
msync, 3-31, 3-46, 4-17, 13-6
mtmsr, 3-40
mtspr, 3-26
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