Index N–R
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Index-9
N
Nap mode, 6-2
see also Power management
No-op, C-24
O
Operands
BO encodings, 3-23
conventions, 3-1
placement and performance, 4-30
P
Page characteristics
see Memory/cache access attributes (WIMGE bits), 1-30
Parity checking, 5-17, 11-8
on internal buses, 13-5
see also Caches, parity checking
Parity errors, see Interrupt handling, interrupt types, machine
check interrupt
Performance
characterizing through performance monitor event
counting, 7-1
Performance monitor APU, 7-1
event counting, 7-10
chaining counters, 7-11
event types, 7-12–7-17
processor context marking, 7-10
setting multiple thresholds, 7-12
time base event, 9-4
unconditional counting, 7-11
examples of uses, 7-11
instructions, 3-60, 7-9
interrupt triggered by events, 5-33, 7-1, 7-10
see also Interrupt handling
overview, 1-30
PMR encodings, 3-61
purposes, 1-5
registers (PMRs), 1-31, 2-52–2-58, 7-2–7-9
Performed loads and stores, 11-14
Permissions
controlled by TLB entries in MMU, 12-7
violations and ISI or DSI interrupts, 12-24
Physical addresses
36-bit physical addresses, 12-31
PID0–2 (process ID registers), 2-36, 12-5, 12-21
Pipeline
see also Execution timing
superscalar diagram, 4-4, 4-5
PIR (processor ID register), 2-12
PLL
disabling for power savings, 6-3
PLRU algorithm, 11-25
see also Caches, operation, block replacement
PMC0–3 (performance monitor counter registers), 2-57, 7-8
PMGC0 (global control register 0), 1-31, 2-53, 7-4
PMLCa0–PMLCa3 (performance monitor local control
registers A, 0–3), 2-55, 7-5
PMLCb0–PMLCb3 (performance monitor local control
registers B, 0–3), 2-56, 7-6
Position-independent code example, 4-45
Power management
control bits, 6-3
core states
full on state, 6-3
halted state, 6-3
stopped state, 6-3
device modes (doze, nap, and sleep), 6-2
dynamic power management, 6-2
interrupt recognition and servicing, 6-6
PLL and timer, disabling, 6-3
protocol between core and other device logic, 6-5
signals, 6-1, 13-5
snooping
maintaining L1 cache coherency in power down mode,
6-3
software considerations, 6-4
PowerPC architecture
legacy support, overview, 1-32
user instruction set (UISA), 1-xxxi
Process ID
registers (PID0–2), 1-28, 2-36, 12-5, 12-21
see also Memory management unit (MMU)
Processor control instructions, 3-26–3-29
Program interrupt, 5-24–5-25
see also Interrupt handling
Program order, definition, 4-2
Programming model
overview, 1-18
register summary, 1-19, 2-1
updating the architectural state of registers, 4-21
PVR (processor version register), 1-5, 2-13
R
Read fault exception enable (RFXE), 2-30, 13-9
Real addresses
36-bit physical addresses, 12-31
see also Memory management unit (MMU)
Registers
branch operations, 2-9–2-10
condition register (CR), 2-9
count register (CTR), 2-10
link register (LR), 2-10
BTB, 10-3
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