PowerPC e500 Core Family Reference Manual, Rev. 1
Index-10 Freescale Semiconductor
S–S Index
branch buffer entry address register (BBEAR), 2-25
branch buffer target address (BBTAR), 2-25
branch unit control and status (BUCSR), 2-26
cache control
L1 cache configuration 0 (L1CFG0), 2-34
L1 cache configuration 1 (L1CFG1), 2-35
debug, 8-1, 8-4
data address compare (DAC1–2), 2-48
debug control registers (DBCR0–2), 2-46
debug status register (DBSR), 2-47
instruction address compare (IAC1–2), 2-48
decrementer auto-reload (DECAR), 2-16, 9-3
decrementer register (DEC), 2-16, 9-3
general-purpose registers 0–31 (GPRn), 2-9
hardware implementation-dependent (HID)
HID0, 2-27, 9-2
HID1, 2-29
integer exception (XER), 2-9
interrupt, 2-17, 5-5–5-7
critical save/restore 0–1 (CSRR0–1), 2-18, 5-5
data exception address (DEAR), 2-18
data exception address register (DEAR), 5-5
debug settings, 8-3
defined by Book E, 2-18
exception syndrome register (ESR), 2-20, 5-5, 5-6
machine check address register (MCAR), 2-22, 5-6, 5-17
machine check save/restore 0–1 (MCSRR0–1), 2-22, 5-6
machine check syndrome (MCSR), 2-23, 5-6, 5-7
machine state register (MSR), 5-6
save/restore 0–1 (SRR0–1), 2-18, 5-5
vector offset registers (IVOR0–IVOR15,
IVOR32–IVOR35), 2-19, 5-5
vector prefix (IVPR32–IVPR47), 2-19, 5-5
MMU, 1-27, 2-35–2-45, 12-25–12-32
configuration
MMU configuration (MMUCFG), 2-37
MMU control and status (MMUCSR0), 2-36
TLB configuration 0–1 (TLBnCFG), 2-37
MMU assist (MAS0–MAS4, MAS6–MAS7), 2-39–2-45
process ID (PID0–2), 2-36
performance monitor, 7-2–7-9
counter registers (PMC0–3), 1-31, 2-57, 7-8
global control 0 (PMGC0), 7-4
global control register 0 (PMGC0), 1-31, 2-53
local control A (PMLCa0–PMLCa3), 2-55, 7-5
local control B (PMLCb0–PMLCb3), 2-56, 7-6
PMR encodings, 3-61
user counter registers (UPMC0–3), 2-58, 7-9
user global control 0 (UPMG0), 2-54
user global control 0 (UPMGC0), 7-5
user local control A (UPMLCa0–UPMLCa3), 2-56, 7-6
user local control B (UPMLCb0–UPMLCb3), 2-57, 7-7
processor control
machine state register (MSR), 2-10
processor ID register (PIR), 2-12
processor version register (PVR), 1-5, 2-13
system version register (SVR), 1-5, 2-13
rename register operation, 4-7, 4-11, 4-15
signal processing engine (SPE) APU
accumulator, 2-52
SPEFSCR, 2-49
special-purpose (SPRs), 2-5, 3-27–3-29
software-use SPRs, USPRG0, 2-24
SPRG0–SPRG7 (software-use SPRs), 2-24
synchronization requirements for SPRs, 2-58, 3-8
time base
TBL and TBU, 2-16
timer control register (TCR), 2-15, 9-2
timer status register (TSR), 2-16, 9-3
Rename buffer, definition, 4-2
Rename registers, 4-7, 4-11, 4-15
see also Execution timing
Reservation stations
and serialization, 4-15
data dependencies, 4-14, 4-47, 4-48
definition, 4-3
flow diagram, 4-5
relationship with issue stage, 4-7, 4-9, 4-10, 4-14, 4-46
stalls for divides, 4-29
Reservations (memory) with lwarx and stwcx., 3-32–3-37,
3-48, 11-15, 13-8
Reset
common vector, 1-34
default TLB entry (MMU), 12-24
reset generation, 5-10
Retirement, definition, 4-3
Return debug event, 8-13
rfci, 3-40
rfi, 3-40
rfmci, 3-40
Rotate/shift instructions, 3-16, C-2
Round-robin replacement algorithm
hints for TLB0, 12-13
S
sc, 3-40
Sequential consistency of memory accesses, 11-15
Serialization instructions, 4-15, 4-47
Shift/rotate instructions, 3-16, C-2
Signal processing engine (SPE) APU
instructions, 3-49, 3-52
execution latencies, 4-38
interrupts, 5-3
registers
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