Index T–T
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Index-11
accumulator, 2-52
SPEFSCR, 2-49
Signals
core complex bus (CCB) internal signals, 13-2
JTAG, 8-5, 8-6, 13-3
power management, 6-1, 13-5
Simplified mnemonics, 3-42
branch instructions, C-4
compare instructions, C-20
CR logical instructions, C-20
recommended, C-24
rotate and shift, C-2
special-purpose registers (SPRs), C-23
subtract instructions, C-2
trap instructions, C-21
Single-precision floating-point (SPFP) APUs
floating-point instructions, 3-58
Sleep mode, 6-2
see also Power management
Snooping
global signaling (and M bit), 11-12
SPE/FP APU unavailable interrupt, 5-31
see also Interrupt handling
Speculative instruction, 4-3
SPEFSCR (SPE floating-point status and control register),
2-49
SPR model
invalid SPR references, 2-5
move to/from SPR instructions, 3-26
simplified mnemonics, C-23
SPR summary, 3-27–3-29
synchronization requirements for SPRs, 2-58
SPRG0–SPRG7 (software-use SPRs), 2-24
SRR0–1 (save/restore registers 0–1), 2-18, 5-5
Stall, definition, 4-3
Stopped state, see Power management, core states
Store instructions, 3-21
Store miss merging
and data cache misses, 11-4, 11-24
stwcx., 3-31, 3-48, 11-15, 13-8
Subtract instructions, C-2
Suggested reading list, 1-xxxiii
Superscalar pipeline
definition, 4-3
e500, 4-5
SVR (system version register), 1-5, 2-13
Synchronization
context synchronization, 3-11, 3-44
execution synchronization, 3-11
general, A-1
memory instructions, 3-30
timing considerations, 4-17–4-18
primitives, A-2
compare and swap, A-4
fetch and add, A-3
fetch and AND, A-3
fetch and no-op, A-2
fetch and store, A-3
requirements for special registers and TLBs, 3-6
requirements for TLB instructions, 3-10
synchronization boundary with msync, 13-6
Synchronization requirements for SPRs, 2-58
System call
system call interrupt, 5-25
see also Interrupt handling
System linkage instructions, 3-26, 3-40
System register execution latencies, 4-31
T
TAP interface
signals, 8-5
TBL and TBU (time base registers), 2-16
TCR (timer control register), 2-15, 9-2
Terminology conventions, 1-xxxv
Test and set function, A-4
Throughput, definition, 4-3
Time base, 2-14–2-16
disabling for power savings, 6-3
e500 implementation, 9-1, 9-3
performance monitor time base event, 9-4
registers
TBL and TBU, 2-16
timer control register (TCR), 2-15, 9-2
timer status register (TSR), 2-16, 9-3
TLB1 and TLB0, see Memory management unit (MMU), L2
TLB arrays
tlbivax, 3-41, 12-20, 12-21
TLBnCFG (TLB configuration registers 0–1), 2-37
tlbre, 3-41, 12-18
TLBs (translation lookaside buffers), 12-8–12-25
coherency, 1-28
entry reload facilities, 12-22
fields on 32-bit Book E implementations, B-2
instructions for managing TLBs, 3-41, 11-11
maintenance features, 12-3
programming model, 12-17–12-24
misses, 12-2, 12-12, 12-20, 12-22, 12-23, 12-24
see also Interrupt handling, TLB error
see also Memory management unit (MMU)
six TLBs, 12-8–12-17
L1 TLB arrays, 12-9
L2 TLB arrays, 12-11
synchronization requirements, 3-6, 3-10
TLB entry field definitions, 12-17
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