PowerPC e500 Core Family Reference Manual, Rev. 1
Index-12 Freescale Semiconductor
U–X Index
TLB miss, see Interrupt handling, interrupt types, TLB
miss
writing to TLBs, 12-19
tlbsx, 3-42, 12-19
tlbsync, 3-42, 12-22
tlbwe, 3-42, 12-19
TO operand, C-23
Trap debug event, 8-11
Trap instructions, 3-25
simplified mnemonics, C-21
True little-endian pages, 2-42
TSR (timer status register), 2-16, 9-3
U
Unconditional debug event (UDE), 8-14
Unsupported instructions and instruction forms, 3-3
Update instructions (load and store), 3-47
UPMC0–3 (user performance monitor counter registers),
2-58, 7-9
UPMGC0 (user global control register 0), 2-54, 7-5
UPMLCa0–UPMLCa3 (user performance monitor local
control A registers), 2-56
UPMLCa0–UPMLCa3 (user performance monitor local
control registers A, 0–3), 7-6
UPMLCb0–UPMLCb3 (user performance monitor local
control B registers), 2-57
UPMLCb0–UPMLCb3 (user performance monitor local
control registers B, 0–3), 7-7
User instruction set architecture (UISA) description, 1-xxxi
USPRG0 (user SPR), 2-24
W
Watchdog timer
watchdog timer interrupt, 5-27
see also Interrupt handling
Weakly ordered memory references, 1-29, 11-14
Write-back
definition, 4-3, 4-8, 4-9
wrtee, 3-40
wrteei, 3-40
X
XER (integer exception register), 2-2, 2-9
To Next Page
Loading...
