PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor Index-1
Index
Numerics
Numerics
36-bit real addressing, 2-45, 12-1, 12-5, 12-8
64-bit–specific Book E instructions, B-1
A
Accumulator
signal processing engine (SPE) APU, 2-52
addi, C-24
addis, C-24
Address streaming mode on CCB, 13-7
Address translation
see Memory management unit (MMU), 1-26
Addresses
36-bit physical addressing, 12-31
Addressing modes
32-bit Book E implementations, B-2
register indirect
integer, 3-19
with immediate index, integer, 3-18
with index, integer, 3-19
Aliasing of addresses, see Caches, coherency
Alignment
misaligned accesses, 3-2
relation to Endian (E) bit, 11-13
natural boundaries for extended vector instructions, 3-44
Alignment interrupt, 5-22
see also Interrupt handling
Arithmetic instructions
integer, 3-5, 3-13
Atomic memory references, 1-29, 3-21
update primitives lwarx and stwcx., 3-32–3-37, 11-15,
13-8
Auxiliary processing units (APUs)
branch target buffer locking APU (BPU), 10-2
see also Branch target buffer (BTB)
cache block lock and unlock APU, 3-61, 11-19, 11-21
embedded double-precision floating-point (DPFP) APU,
3-49, 3-59
embedded single-precision floating-point (SPFP) APUs,
3-2, 3-58, 5-3
isel (instruction select) APU, 3-25, 3-60
machine check interrupt APU, 3-63, 5-2
see also Interrupt handling, interrupt types, machine
check interrupt
performance monitor APU, 3-60, 3-61, 5-33, 7-2
signal processing engine (SPE) APU, 3-49, 3-52, 5-3
B
BBEAR (branch buffer entry address register), 2-25
bbelr, 3-64
bblels, 3-65
BBTAR (branch buffer target address register), 2-25
Block diagram
e500 core complex, 1-2
BO encodings, 3-23
Book E architecture
32-bit addressing, B-3
32-bit instruction selection, B-3
auxiliary processing units (APUs), 1-3
debug model
debug model deviations, 8-3
events defined, 8-6
future upward compatibility and SPE APU, 1-3
instruction listing, 3-66
instructions with implementation-specific features, 3-43
interrupt and exception model, 5-1
exception priorities, 5-37–5-39
interrupt registers, 2-18, 5-5–5-6
terminology definitions, 5-1
supervisor-level instructions in the e500, 3-39
user-level instructions, 3-13
Boundedly undefined, definition, 3-6
Branch instructions
BO operand encodings, 3-23
condition register logical, 3-25, C-20
control of conditional branches, 3-23
list, 3-24
simplified mnemonics list, C-4, C-12, C-16
system linkage, 3-26, 3-40
trap, 3-25
Branch issue queue (BIQ), 4-6, 4-46
Branch registers, 2-9–2-10
condition register (CR), 2-9
count register (CTR), 2-10
link register (LR), 2-10
speculative copies of LR and CTR, 4-15
Branch target buffer (BTB)
branch unit control and status register (BUCSR), 2-26
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