Core Complex Overview
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 1-13
— SPE APU vector instructions. Vector instructions are defined that view the 64-bit GPRs
as composed of a vector of two 32-bit elements (some instructions also read or write
16-bit elements). Some scalar instructions produce a 64-bit scalar result.
Section 3.8.1.3, “SPE APU Instructions,” lists SPE APU vector instructions.
— The embedded floating-point APUs provide scalar and vector floating-point
instructions. Scalar single-precision floating-point instructions use only the lower 32
bits of the GPRs; double-precision operands (e500v2 only) use all 64 bits. Table 1-4
lists embedded floating-point instructions.
— BTB locking APU instructions. The core complex provides a 512-entry BTB for
efficient processing of branch instructions. The BTB is a branch target address cache,
Table 1-4. Scalar and Vector Embedded Floating-Point APU Instructions
Instruction
Mnemonic
Syntax
Scalar SP Scalar DP Vector
Convert Floating-Point Single- from Double-Precision —efscfd — rD,rB
Convert Floating-Point Double- from Single-Precision —efdcfs — rD,rB
Convert Floating-Point from Signed Fraction efscfsf efdcfsf evfscfsf rD,rB
Convert Floating-Point from Signed Fraction efscfsf efdcfsf evfscfsf rD,rB
Convert Floating-Point from Signed Integer efscfsi efdcfsi evfscfsi rD,rB
Convert Floating-Point from Unsigned Fraction efscfuf efdcfuf evfscfuf rD,rB
Convert Floating-Point from Unsigned Integer efscfui efdcfui evfscfui rD,rB
Convert Floating-Point to Signed Fraction efsctsf efdctsf evfsctsf rD,rB
Convert Floating-Point to Signed Integer efsctsi efdctsi evfsctsi rD,rB
Convert Floating-Point to Signed Integer with Round toward Zero efsctsiz efdctsiz evfsctsiz rD,rB
Convert Floating-Point to Unsigned Fraction efsctuf efdctuf evfsctuf rD,rB
Convert Floating-Point to Unsigned Integer efsctui efdctui evfsctui rD,rB
Convert Floating-Point to Unsigned Integer with Round toward Zero efsctuiz efdctuiz evfsctuiz rD,rB
Floating-Point Absolute Value efsabs efdabs evfsabs rD,rA
Floating-Point Add efsadd efdadd evfsadd rD,rA,rB
Floating-Point Compare Equal efscmpeq efdcmpeq evfscmpeq crD,rA,rB
Floating-Point Compare Greater Than efscmpgt efdcmpgt evfscmpgt crD,rA,rB
Floating-Point Compare Less Than efscmplt efdcmplt evfscmplt crD,rA,r
B
Floating-Point Divide efsdiv efddiv evfsdiv rD,rA,rB
Floating-Point Multiply efsmul efdmul evfsmul rD,rA,rB
Floating-Point Negate efsneg efdneg evfsneg rD,rA
Floating-Point Negative Absolute Value efsnabs efdnabs evfsnabs rD,rA
Floating-Point Subtract efssub efdsub evfssub rD,rA,rB
Floating-Point Test Equal efststeq efdtsteq evfststeq crD,rA,rB
Floating-Point Test Greater Than efststgt efdtstgt evfststgt crD,rA,rB
Floating-Point Test Less Than efststlt efdtstlt evfststlt crD,rA,rB
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