Freescale Semiconductor PowerPC e500 Core - Page 301

Performance Monitor
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 7-3
The user-level performance monitor registers in Table 7-2 are read-only and are accessed with the
mfpmr instruction. Attempting to write these user-level registers in either supervisor or user mode
causes an illegal instruction exception.
145 00100 10001 Performance monitor local control a1 PMLCa1
146 00100 10010 Performance monitor local control a2 PMLCa2
147 00100 10011 Performance monitor local control a3 PMLCa3
272 01000 10000 Performance monitor local control b0 PMLCb0
273 01000 10001 Performance monitor local control b1 PMLCb1
274 01000 10010 Performance monitor local control b2 PMLCb2
275 01000 10011 Performance monitor local control b3 PMLCb3
400 01100 10000 Performance monitor global control 0 PMGC0
Table 7-2. Performance Monitor Registers–User Level (Read-Only)
Number PMR[0–4] PMR[5–9] Name Abbreviation
0 00000 00000 Performance monitor counter 0 UPMC0
1 00000 00001 Performance monitor counter 1 UPMC1
2 00000 00010 Performance monitor counter 2 UPMC2
3 00000 00011 Performance monitor counter 3 UPMC3
128 00100 00000 Performance monitor local control a0 UPMLCa0
129 00100 00001 Performance monitor local control a1 UPMLCa1
130 00100 00010 Performance monitor local control a2 UPMLCa2
131 00100 00011 Performance monitor local control a3 UPMLCa3
256 01000 00000 Performance monitor local control b0 UPMLCb0
257 01000 00001 Performance monitor local control b1 UPMLCb1
258 01000 00010 Performance monitor local control b2 UPMLCb2
259 01000 00011 Performance monitor local control b3 UPMLCb3
384 01100 00000 Performance monitor global control 0 UPMGC0
Table 7-1. Performance Monitor Registers–Supervisor Level (continued)
Number PMR[0–4] PMR[5–9] Name Abbreviation