PowerPC e500 Core Family Reference Manual, Rev. 1
1-10 Freescale Semiconductor
Core Complex Overview
– Interrupt vector offset registers (IVORs) 0–15 as defined in Book E, plus
e500-defined IVORs 32–35
– Exception syndrome register (ESR)
– Book E-defined preempting critical interrupt, including critical interrupt status
registers (CSRR0 and CSRR1) and an rfci instruction
— e500-specific interrupts not defined in Book E architecture
– Machine-check APU
– SPE APU unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor
• Memory management unit (MMU)
— 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual
address) for the e500v1core and 36-bit real addressing for the e500v2 core
— TLB entries for variable- (4-Kbyte–256-Mbyte pages for the e500v1 and
4-Kbyte–4-Gbyte pages for the e500v2) and fixed-size (4-Kbyte) pages
— Data L1 MMU
– 4-entry, fully associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages
— Instruction L1 MMU
– 4-entry, fully associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages
— Unified L2 MMU
– 16-entry, fully associative TLB array for variable-sized pages
– e500v1—A 256-entry, 2-way set-associative unified (for instruction and data
accesses) L2 TLB array (TLB0) supports only 4-Kbyte pages
– e500v2—A 512-entry, 4-way set-associative unified (for instruction and data
accesses) L2 TLB array (TLB0) supports only 4-Kbyte pages
— Software reload for TLBs
— Virtual memory support for as much as 4 Gbytes (2
32
) of effective address space
— Real memory support for as much as 4 Gbytes (2
32
) of physical memory on the e500v1
and 64 Gbytes (2
36
) on the e500v2
— Support for big-endian and true little-endian memory on a per-page basis
• Power management
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