Freescale Semiconductor PowerPC e500 Core - Page 7

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor vii
Contents
Paragraph
Number Title
Page
Number
2.6 Timer Registers..............................................................................................................2-14
2.6.1 Timer Control Register (TCR)................................................................................... 2-15
2.6.2 Timer Status Register (TSR)...................................................................................... 2-16
2.6.3 Time Base (TBU and TBL) ....................................................................................... 2-16
2.6.4 Decrementer Register (DEC)..................................................................................... 2-16
2.6.5 Decrementer Auto-Reload Register (DECAR)..........................................................2-16
2.6.6 Alternate Time Base Registers (ATBL and ATBU)................................................... 2-16
2.6.6.1 Alternate Time Base Upper (ATBU) ..................................................................... 2-17
2.7 Interrupt Registers..........................................................................................................2-17
2.7.1 Interrupt Registers Defined by Book E...................................................................... 2-18
2.7.1.1 Save/Restore Register 0/1 (SRR0 and SRR1) ....................................................... 2-18
2.7.1.2 Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)..................................... 2-18
2.7.1.3 Data Exception Address Register (DEAR)............................................................ 2-18
2.7.1.4 Interrupt Vector Prefix Register (IVPR)................................................................ 2-19
2.7.1.5 Interrupt Vector Offset Registers (IVORs) ............................................................ 2-19
2.7.1.6 Exception Syndrome Register (ESR) .................................................................... 2-20
2.7.2 e500-Specific Interrupt Registers .............................................................................. 2-22
2.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)...........................................2-22
2.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)...........................................2-22
2.7.2.3 Machine Check Address Register (MCAR) .......................................................... 2-22
2.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 2-23
2.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 2-24
2.9 Branch Target Buffer (BTB) Registers .......................................................................... 2-24
2.9.1 Branch Buffer Entry Address Register (BBEAR) ..................................................... 2-25
2.9.2 Branch Buffer Target Address Register (BBTAR).................................................... 2-25
2.9.3 Branch Unit Control and Status Register (BUCSR).................................................. 2-26
2.10 Hardware Implementation-Dependent Registers........................................................... 2-27
2.10.1 Hardware Implementation-Dependent Register 0 (HID0).........................................2-27
2.10.2 Hardware Implementation-Dependent Register 1 (HID1).........................................2-29
2.11 L1 Cache Configuration Registers................................................................................. 2-31
2.11.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 2-31
2.11.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 2-33
2.11.3 L1 Cache Configuration Register 0 (L1CFG0) .........................................................2-34
2.11.4 L1 Cache Configuration Register 1 (L1CFG1) .........................................................2-35
2.12 MMU Registers.............................................................................................................. 2-35
2.12.1 Process ID Registers (PID0–PID2)............................................................................ 2-36
2.12.2 MMU Control and Status Register 0 (MMUCSR0).................................................. 2-36
2.12.3 MMU Configuration Register (MMUCFG) .............................................................. 2-37