PowerPC e500 Core Family Reference Manual, Rev. 1
viii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
2.12.4 TLB Configuration Registers (TLBnCFG) ............................................................... 2-37
2.12.4.1 TLB0 Configuration Register (TLB0CFG)........................................................... 2-38
2.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................2-39
2.12.5 MMU Assist Registers (MAS0–MAS4, MAS6–MAS7) .......................................... 2-39
2.12.5.1 MAS Register 0 (MAS0)....................................................................................... 2-40
2.12.5.2 MAS Register 1 (MAS1)....................................................................................... 2-41
2.12.5.3 MAS Register 2 (MAS2)....................................................................................... 2-42
2.12.5.4 MAS Register 3 (MAS3)....................................................................................... 2-43
2.12.5.5 MAS Register 4 (MAS4)....................................................................................... 2-43
2.12.5.6 MAS Register 6 (MAS6)....................................................................................... 2-44
2.12.5.7 MAS Register 7 (MAS7)—e500v2 Only .............................................................. 2-45
2.13 Debug Registers.............................................................................................................2-45
2.13.1 Debug Control Registers (DBCR0–DBCR2) ............................................................ 2-46
2.13.1.1 Debug Control Register 0 (DBCR0)...................................................................... 2-46
2.13.1.2 Debug Control Register 1 (DBCR1)...................................................................... 2-46
2.13.1.3 Debug Control Register 2 (DBCR2)...................................................................... 2-47
2.13.2 Debug Status Register (DBSR).................................................................................. 2-47
2.13.3 Instruction Address Compare Registers (IAC1–IAC4)............................................. 2-48
2.13.4 Data Address Compare Registers (DAC1–DAC2).................................................... 2-48
2.14 SPE and SPFP APU Registers....................................................................................... 2-49
2.14.1 Signal Processing and Embedded Floating-Point Status and Control
Register (SPEFSCR).............................................................................................. 2-49
2.14.2 Accumulator (ACC)................................................................................................... 2-52
2.15 Performance Monitor Registers (PMRs) ....................................................................... 2-52
2.15.1 Global Control Register 0 (PMGC0)......................................................................... 2-53
2.15.2 User Global Control Register 0 (UPMGC0).............................................................. 2-54
2.15.3 Local Control A Registers (PMLCa0–PMLCa3) ...................................................... 2-55
2.15.4 User Local Control A Registers (UPMLCa0–UPMLCa3)........................................ 2-56
2.15.5 Local Control B Registers (PMLCb0–PMLCb3)...................................................... 2-56
2.15.6 User Local Control B Registers (UPMLCb0–UPMLCb3)........................................ 2-57
2.15.7 Performance Monitor Counter Registers (PMC0–PMC3).........................................2-57
2.15.8 User Performance Monitor Counter Registers (UPMC0–UPMC3) .......................... 2-58
2.16 Synchronization Requirements for SPRs....................................................................... 2-58
Chapter 3
Instruction Model
3.1 Operand Conventions ...................................................................................................... 3-1
3.1.1 Data Organization in Memory and Data Transfers......................................................3-1
3.1.2 Alignment and Misaligned Accesses........................................................................... 3-2
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