Freescale Semiconductor PowerPC e500 Core - Page 9

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor ix
Contents
Paragraph
Number Title
Page
Number
3.1.3 e500 Floating-Point Implementation ........................................................................... 3-2
3.1.4 Unsupported Book E Instructions................................................................................ 3-3
3.2 Instruction Set Summary ................................................................................................. 3-5
3.2.1 Classes of Instructions ................................................................................................. 3-6
3.2.2 Definition of Boundedly Undefined............................................................................ 3-6
3.2.3 Synchronization Requirements.................................................................................... 3-6
3.2.3.1 Synchronization Requirements for e500-Specific SPRs .........................................3-8
3.2.3.2 Synchronization with tlbwe and tlbivax Instructions...........................................3-10
3.2.3.3 Context Synchronization ....................................................................................... 3-11
3.2.3.4 Execution Synchronization.................................................................................... 3-11
3.2.3.5 Instruction-Related Interrupts................................................................................ 3-12
3.3 Instruction Set Overview ............................................................................................... 3-13
3.3.1 Book E User-Level Instructions ................................................................................ 3-13
3.3.1.1 Integer Instructions................................................................................................ 3-13
3.3.1.1.1 Integer Arithmetic Instructions.......................................................................... 3-13
3.3.1.1.2 Integer Compare Instructions ............................................................................ 3-15
3.3.1.1.3 Integer Logical Instructions............................................................................... 3-15
3.3.1.1.4 Integer Rotate and Shift Instructions................................................................. 3-16
3.3.1.2 Load and Store Instructions ................................................................................... 3-17
3.3.1.2.1 Self-Modifying Code......................................................................................... 3-17
3.3.1.2.2 Integer Load and Store Address Generation...................................................... 3-18
3.3.1.2.3 Integer Load Instructions................................................................................... 3-20
3.3.1.2.4 Integer Store Instructions................................................................................... 3-21
3.3.1.2.5 Integer Load and Store with Byte-Reverse Instructions.................................... 3-22
3.3.1.2.6 Integer Load and Store Multiple Instructions.................................................... 3-22
3.3.1.3 Branch and Flow Control Instructions................................................................... 3-23
3.3.1.3.1 Conditional Branch Control............................................................................... 3-23
3.3.1.3.2 Branch Instructions............................................................................................ 3-24
3.3.1.3.3 Condition Register Logical Instructions............................................................ 3-25
3.3.1.3.4 Trap Instructions................................................................................................ 3-25
3.3.1.4 System Linkage Instruction ................................................................................... 3-26
3.3.1.5 Processor Control Instructions............................................................................... 3-26
3.3.1.5.1 Move to/from Condition Register Instructions.................................................. 3-26
3.3.1.5.2 Move to/from Special-Purpose Register Instructions........................................ 3-26
3.3.1.6 Memory Synchronization Instructions .................................................................. 3-30
3.3.1.6.1 mbar (MO = 1).................................................................................................. 3-31
3.3.1.7 Atomic Update Primitives Using lwarx and stwcx............................................... 3-32
3.3.1.7.1 Reservations....................................................................................................... 3-34
3.3.1.7.2 Forward Progress............................................................................................... 3-36
3.3.1.7.3 Reservation Loss Due to Granularity ................................................................ 3-36