Freescale Semiconductor PowerPC e500 Core - Page 10

PowerPC e500 Core Family Reference Manual, Rev. 1
x Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
3.3.1.8 Memory Control Instructions ................................................................................ 3-37
3.3.1.8.1 User-Level Cache Instructions .......................................................................... 3-37
3.3.2 Supervisor-Level Instructions.................................................................................... 3-39
3.3.2.1 System Linkage Instructions.................................................................................. 3-39
3.3.2.2 Supervisor-Level Memory Control Instructions.................................................... 3-40
3.3.2.2.1 Supervisor-Level Cache Instruction .................................................................. 3-40
3.3.2.2.2 Supervisor-Level TLB Management Instructions.............................................3-41
3.3.3 Recommended Simplified Mnemonics...................................................................... 3-42
3.3.4 Book E Instructions with Implementation-Specific Features.................................... 3-43
3.3.5 e500 Instructions........................................................................................................ 3-43
3.3.6 Context Synchronization............................................................................................ 3-44
3.4 Memory Access Alignment Support.............................................................................. 3-44
3.5 Using msync and mbar to Order Memory Accesses.................................................... 3-45
3.5.1 Lock Acquisition and Import Barriers....................................................................... 3-45
3.5.1.1 Acquire Lock and Import Shared Memory............................................................ 3-45
3.5.1.2 Obtain Pointer and Import Shared Memory .......................................................... 3-45
3.5.1.3 Lock Release and Export Barriers......................................................................... 3-46
3.5.1.3.1 Export Shared Memory and Release Lock........................................................ 3-46
3.5.1.3.2 Export Shared Memory and Release Lock using mbar (MO = 0).................... 3-47
3.5.2 Safe Fetch ..................................................................................................................3-47
3.6 Update Instructions........................................................................................................ 3-47
3.7 Memory Synchronization .............................................................................................. 3-48
3.8 EIS-Defined Instructions and APUs Implemented on the e500 .................................... 3-48
3.8.1 SPE and Embedded Floating-Point APUs................................................................. 3-49
3.8.1.1 SPE Operands: Signed Fractions........................................................................... 3-51
3.8.1.2 SPE Integer and Fractional Operations.................................................................. 3-52
3.8.1.3 SPE APU Instructions............................................................................................ 3-52
3.8.1.4 Embedded Floating-Point APU Instructions .........................................................3-58
3.8.2 Integer Select (isel) APU........................................................................................... 3-60
3.8.3 Performance Monitor APU........................................................................................ 3-60
3.8.4 Cache Locking APU.................................................................................................. 3-61
3.8.5 Machine Check APU ................................................................................................. 3-63
3.9 e500-Specific Instructions ............................................................................................. 3-63
3.9.1 Branch Target Buffer (BTB) Locking Instructions.................................................... 3-63
3.10 Instruction Listing.......................................................................................................... 3-66