Freescale Semiconductor PowerPC e500 Core - Page 11

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xi
Contents
Paragraph
Number Title
Page
Number
Chapter 4
Execution Timing
4.1 Terminology and Conventions......................................................................................... 4-1
4.2 Instruction Timing Overview........................................................................................... 4-4
4.3 General Timing Considerations ..................................................................................... 4-10
4.3.1 General Instruction Flow ........................................................................................... 4-11
4.3.2 Instruction Fetch Timing Considerations................................................................... 4-12
4.3.2.1 L1 and L2 TLB Access Times............................................................................... 4-12
4.3.2.2 Interrupts Associated with Instruction Fetching.................................................... 4-12
4.3.2.3 Cache-Related Latency.......................................................................................... 4-13
4.3.3 Dispatch, Issue, and Completion Considerations ...................................................... 4-14
4.3.3.1 GPR and CR Rename Register Operation ............................................................. 4-15
4.3.3.2 LR and CTR Shadow (Speculative) Registers....................................................... 4-15
4.3.3.3 Instruction Serialization......................................................................................... 4-15
4.3.4 Interrupt Latency........................................................................................................ 4-16
4.3.5 Memory Synchronization Timing Considerations.....................................................4-17
4.3.5.1 msync Instruction Timing Considerations ............................................................ 4-17
4.3.5.2 mbar Instruction Timing Considerations.............................................................. 4-17
4.4 Execution ....................................................................................................................... 4-18
4.4.1 Branch Unit Execution............................................................................................... 4-18
4.4.1.1 Branch Instructions and Completion ..................................................................... 4-18
4.4.1.2 BTB Branch Prediction and Resolution ................................................................ 4-20
4.4.1.3 BTB Operations..................................................................................................... 4-21
4.4.1.3.1 BTB Locking ..................................................................................................... 4-23
4.4.1.3.2 BTB Locking APU Programming Model.......................................................... 4-24
4.4.1.3.3 BTB Operations Controlled by BUCSR............................................................ 4-24
4.4.1.3.4 BTB Special Cases—Phantom Branches and Multiple Matches...................... 4-25
4.4.2 Load/Store Unit Execution ........................................................................................ 4-25
4.4.2.1 Load/Store Unit Queueing Structures.................................................................... 4-25
4.4.3 Simple and Multiple Unit Execution......................................................................... 4-27
4.4.3.1 MU Divide Execution............................................................................................ 4-28
4.4.3.2 MU Floating-Point Execution................................................................................ 4-29
4.4.4 Load/Store Execution ................................................................................................ 4-29
4.4.4.1 Effect of Operand Placement on Performance ...................................................... 4-30
4.5 Memory Performance Considerations ........................................................................... 4-30
4.6 Instruction Latency Summary........................................................................................ 4-31