Freescale Semiconductor PowerPC e500 Core - Page 12

PowerPC e500 Core Family Reference Manual, Rev. 1
xii Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
4.7 Instruction Scheduling Guidelines................................................................................. 4-44
4.7.1 Fetch/Branch Considerations..................................................................................... 4-45
4.7.1.1 Dynamic Prediction versus No Branch Prediction................................................ 4-45
4.7.1.1.1 Position-Independent Code................................................................................ 4-45
4.7.2 Dispatch Unit Resource Requirements...................................................................... 4-45
4.7.2.1 Dispatch Groupings ............................................................................................... 4-46
4.7.3 Issue Queue Resource Requirements......................................................................... 4-46
4.7.3.1 General Issue Queue (GIQ) ................................................................................... 4-46
4.7.3.2 Branch Issue Queue (BIQ)..................................................................................... 4-46
4.7.4 Completion Unit Resource Requirements ................................................................. 4-46
4.7.4.1 Completion Groupings........................................................................................... 4-47
4.7.5 Serialization Effects................................................................................................... 4-47
4.7.6 Execution Unit Considerations.................................................................................. 4-47
4.7.6.1 SU Considerations ................................................................................................. 4-47
4.7.6.2 MU Considerations................................................................................................ 4-48
4.7.6.3 LSU Considerations............................................................................................... 4-48
4.7.6.3.1 Load/Store Interaction ....................................................................................... 4-48
4.7.6.3.2 Misalignment Effects......................................................................................... 4-49
4.7.6.3.3 Load Miss Pipeline ............................................................................................ 4-50
Chapter 5
Interrupts and Exceptions
5.1 Overview.......................................................................................................................... 5-1
5.2 e500 Interrupt Definitions................................................................................................ 5-2
5.2.1 Recoverability from Interrupts..................................................................................... 5-4
5.3 Interrupt Registers............................................................................................................ 5-5
5.4 Exceptions........................................................................................................................ 5-8
5.5 Interrupt Classes ..............................................................................................................5-9
5.5.1 Requirements for System Reset Generation.............................................................. 5-10
5.6 Interrupt Processing ....................................................................................................... 5-10
5.7 Interrupt Definitions ...................................................................................................... 5-12
5.7.1 Critical Input Interrupt............................................................................................... 5-13
5.7.2 Machine Check Interrupt ........................................................................................... 5-14
5.7.2.1 Core Complex Bus (CCB) and L1 Cache Machine Check Errors......................... 5-16
5.7.2.2 Cache Parity Error Injection.................................................................................. 5-18
5.7.3 Data Storage Interrupt................................................................................................ 5-19
5.7.4 Instruction Storage Interrupt...................................................................................... 5-20
5.7.5 External Input Interrupt ............................................................................................. 5-21
5.7.6 Alignment Interrupt ................................................................................................... 5-22