Freescale Semiconductor PowerPC e500 Core - Page 13

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xiii
Contents
Paragraph
Number Title
Page
Number
5.7.7 Program Interrupt....................................................................................................... 5-24
5.7.8 System Call Interrupt................................................................................................. 5-25
5.7.9 Decrementer Interrupt................................................................................................ 5-25
5.7.10 Fixed-Interval Timer Interrupt................................................................................... 5-26
5.7.11 Watchdog Timer Interrupt.......................................................................................... 5-27
5.7.12 Data TLB Error Interrupt........................................................................................... 5-27
5.7.13 Instruction TLB Error Interrupt................................................................................. 5-29
5.7.14 Debug Interrupt.......................................................................................................... 5-30
5.7.15 EIS-Defined Interrupts............................................................................................... 5-31
5.7.15.1 SPE/Embedded Floating-Point APU Unavailable Interrupt.................................. 5-31
5.7.15.2 Embedded Floating-Point Data Interrupt .............................................................. 5-32
5.7.15.3 Embedded Floating-Point Round Interrupt ...........................................................5-32
5.8 Performance Monitor Interrupt...................................................................................... 5-33
5.9 Partially Executed Instructions ...................................................................................... 5-33
5.10 Interrupt Ordering and Masking .................................................................................... 5-35
5.10.1 Guidelines for System Software ................................................................................ 5-36
5.10.2 Interrupt Order...........................................................................................................5-37
5.11 Exception Priorities........................................................................................................5-37
5.11.1 e500 Exception Priorities........................................................................................... 5-39
5.12 e500 Interrupt Latency................................................................................................... 5-39
5.13 Guarded Load and Cache-Inhibited stwcx. Instructions .............................................. 5-40
Chapter 6
Power Management
6.1 Overview.......................................................................................................................... 6-1
6.2 Power Management Signals............................................................................................. 6-1
6.3 Core and Integrated Device Power Management States.................................................. 6-2
6.4 Power Management Control Bits..................................................................................... 6-3
6.4.1 Software Considerations for Power Management.......................................................6-4
6.5 Power Management Protocol........................................................................................... 6-5
6.6 Interrupts and Power Management.................................................................................. 6-6
Chapter 7
Performance Monitor
7.1 Overview.......................................................................................................................... 7-1
7.2 Performance Monitor APU Registers.............................................................................. 7-2
7.2.1 Global Control Register 0 (PMGC0)........................................................................... 7-4
7.2.2 User Global Control Register 0 (UPMGC0)................................................................ 7-5