Freescale Semiconductor PowerPC e500 Core - Page 14

PowerPC e500 Core Family Reference Manual, Rev. 1
xiv Freescale Semiconductor
Contents
Paragraph
Number Title
Page
Number
7.2.3 Local Control A Registers (PMLCa0–PMLCa3) ........................................................ 7-5
7.2.4 User Local Control A Registers (UPMLCa0–UPMLCa3).......................................... 7-6
7.2.5 Local Control B Registers (PMLCb0–PMLCb3)........................................................ 7-6
7.2.6 User Local Control B Registers (UPMLCb0–UPMLCb3).......................................... 7-7
7.2.7 Performance Monitor Counter Registers (PMC0–PMC3)........................................... 7-8
7.2.8 User Performance Monitor Counter Registers (UPMC0–UPMC3)............................ 7-9
7.3 Performance Monitor APU Instructions.......................................................................... 7-9
7.4 Performance Monitor Interrupt...................................................................................... 7-10
7.5 Event Counting .............................................................................................................. 7-10
7.5.1 Processor Context Configurability............................................................................. 7-10
7.6 Examples........................................................................................................................ 7-11
7.6.1 Chaining Counters ..................................................................................................... 7-11
7.6.2 Thresholding .............................................................................................................. 7-12
7.7 Event Selection ..............................................................................................................7-12
Chapter 8
Debug Support
8.1 Overview.......................................................................................................................... 8-1
8.2 Programming Model........................................................................................................ 8-1
8.2.1 Register Set.................................................................................................................. 8-1
8.2.2 Instruction Set..............................................................................................................8-2
8.2.3 Debug Interrupt Model ................................................................................................ 8-2
8.2.4 Deviations from the Book E Debug Model................................................................. 8-3
8.2.5 Hardware Facilities...................................................................................................... 8-4
8.3 TAP Controller and Register Model ................................................................................ 8-4
8.3.1 TAP Interface Signals.................................................................................................. 8-5
8.4 Book E Debug Events...................................................................................................... 8-6
8.4.1 Instruction Address Compare Debug Event ................................................................ 8-7
8.4.1.1 Instruction Address Compare User and Supervisor Modes..................................... 8-7
8.4.1.2 Effective Address Mode .......................................................................................... 8-8
8.4.1.3 Instruction Address Compare Mode........................................................................ 8-8
8.4.2 Data Address Compare Debug Event.......................................................................... 8-9
8.4.2.1 Data Address Compare Read/Write Enable.............................................................8-9
8.4.2.2 Data Address Compare User/Supervisor Mode.....................................................8-10
8.4.2.3 Effective Address Mode ........................................................................................ 8-10
8.4.2.4 Data Address Compare (DAC) Mode.................................................................... 8-10
8.4.3 Trap Debug Event...................................................................................................... 8-11
8.4.4 Branch Taken Debug Event ....................................................................................... 8-12
8.4.5 Instruction Complete Debug Event............................................................................ 8-12